diff --git a/cpu/samd21/periph/rtt.c b/cpu/samd21/periph/rtt.c
index 8919f43d83..b779eb64d9 100644
--- a/cpu/samd21/periph/rtt.c
+++ b/cpu/samd21/periph/rtt.c
@@ -117,7 +117,7 @@ void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
 
     /* Enable Overflow Interrupt and clear flag */
     RtcMode0 *rtcMode0 = &(RTT_DEV);
-    rtcMode0->INTFLAG.bit.OVF = 1;
+    rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
     rtcMode0->INTENSET.bit.OVF = 1;
 }
 
@@ -155,7 +155,7 @@ void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
     while (rtcMode0->STATUS.bit.SYNCBUSY) {}
 
     /* Enable Compare Interrupt and clear flag */
-    rtcMode0->INTFLAG.bit.CMP0 = 1;
+    rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0;
     rtcMode0->INTENSET.bit.CMP0 = 1;
 }
 
@@ -196,12 +196,12 @@ void RTT_ISR(void)
 
     if ( (status & RTC_MODE0_INTFLAG_CMP0) && (rtt_callback.alarm_cb != NULL) ) {
         rtt_callback.alarm_cb(rtt_callback.alarm_arg);
-        rtcMode0->INTFLAG.bit.CMP0 = 1;
+        rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_CMP0;
     }
 
     if ( (status & RTC_MODE0_INTFLAG_OVF) && (rtt_callback.overflow_cb != NULL) ) {
         rtt_callback.overflow_cb(rtt_callback.overflow_arg);
-        rtcMode0->INTFLAG.bit.OVF = 1;
+        rtcMode0->INTFLAG.reg |= RTC_MODE0_INTFLAG_OVF;
     }
 
     cortexm_isr_end();
diff --git a/cpu/samd21/periph/timer.c b/cpu/samd21/periph/timer.c
index 8b2738a187..d4d530bcba 100644
--- a/cpu/samd21/periph/timer.c
+++ b/cpu/samd21/periph/timer.c
@@ -142,12 +142,12 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
         /* set timeout value */
         switch (channel) {
         case 0:
-            TIMER_0_DEV.INTFLAG.bit.MC0 = 1;
+            TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC0;
             TIMER_0_DEV.CC[0].reg = value;
             TIMER_0_DEV.INTENSET.bit.MC0 = 1;
             break;
         case 1:
-            TIMER_0_DEV.INTFLAG.bit.MC1 = 1;
+            TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC1;
             TIMER_0_DEV.CC[1].reg = value;
             TIMER_0_DEV.INTENSET.bit.MC1 = 1;
             break;
@@ -161,12 +161,12 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
         /* set timeout value */
         switch (channel) {
         case 0:
-            TIMER_1_DEV.INTFLAG.bit.MC0 = 1;
+            TIMER_1_DEV.INTFLAG.reg |= TC_INTFLAG_MC0;
             TIMER_1_DEV.CC[0].reg = value;
             TIMER_1_DEV.INTENSET.bit.MC0 = 1;
             break;
         case 1:
-            TIMER_1_DEV.INTFLAG.bit.MC1 = 1;
+            TIMER_1_DEV.INTFLAG.reg |= TC_INTFLAG_MC1;
             TIMER_1_DEV.CC[1].reg = value;
             TIMER_1_DEV.INTENSET.bit.MC1 = 1;
             break;
@@ -191,11 +191,11 @@ int timer_clear(tim_t dev, int channel)
     case TIMER_0:
         switch (channel) {
         case 0:
-            TIMER_0_DEV.INTFLAG.bit.MC0 = 1;
+            TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC0;
             TIMER_0_DEV.INTENCLR.bit.MC0 = 1;
             break;
         case 1:
-            TIMER_0_DEV.INTFLAG.bit.MC1 = 1;
+            TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC1;
             TIMER_0_DEV.INTENCLR.bit.MC1 = 1;
             break;
         default:
@@ -207,11 +207,11 @@ int timer_clear(tim_t dev, int channel)
     case TIMER_1:
         switch (channel) {
         case 0:
-            TIMER_1_DEV.INTFLAG.bit.MC0 = 1;
+            TIMER_1_DEV.INTFLAG.reg |= TC_INTFLAG_MC0;
             TIMER_1_DEV.INTENCLR.bit.MC0 = 1;
             break;
         case 1:
-            TIMER_1_DEV.INTFLAG.bit.MC1 = 1;
+            TIMER_1_DEV.INTFLAG.reg |= TC_INTFLAG_MC1;
             TIMER_1_DEV.INTENCLR.bit.MC1 = 1;
             break;
         default:
@@ -310,14 +310,14 @@ void TIMER_0_ISR(void)
 {
     if (TIMER_0_DEV.INTFLAG.bit.MC0 && TIMER_0_DEV.INTENSET.bit.MC0) {
         if(config[TIMER_0].cb) {
-            TIMER_0_DEV.INTFLAG.bit.MC0 = 1;
+            TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC0;
             TIMER_0_DEV.INTENCLR.reg = TC_INTENCLR_MC0;
             config[TIMER_0].cb(config[TIMER_0].arg, 0);
         }
     }
     else if (TIMER_0_DEV.INTFLAG.bit.MC1 && TIMER_0_DEV.INTENSET.bit.MC1) {
         if(config[TIMER_0].cb) {
-            TIMER_0_DEV.INTFLAG.bit.MC1 = 1;
+            TIMER_0_DEV.INTFLAG.reg |= TC_INTFLAG_MC1;
             TIMER_0_DEV.INTENCLR.reg = TC_INTENCLR_MC1;
             config[TIMER_0].cb(config[TIMER_0].arg, 1);
         }
@@ -333,14 +333,14 @@ void TIMER_1_ISR(void)
 {
     if (TIMER_1_DEV.INTFLAG.bit.MC0 && TIMER_1_DEV.INTENSET.bit.MC0) {
         if (config[TIMER_1].cb) {
-            TIMER_1_DEV.INTFLAG.bit.MC0 = 1;
+            TIMER_1_DEV.INTFLAG.reg |= TC_INTFLAG_MC0;
             TIMER_1_DEV.INTENCLR.reg = TC_INTENCLR_MC0;
             config[TIMER_1].cb(config[TIMER_1].arg, 0);
         }
     }
     else if (TIMER_1_DEV.INTFLAG.bit.MC1 && TIMER_1_DEV.INTENSET.bit.MC1) {
         if(config[TIMER_1].cb) {
-            TIMER_1_DEV.INTFLAG.bit.MC1 = 1;
+            TIMER_1_DEV.INTFLAG.reg |= TC_INTFLAG_MC1;
             TIMER_1_DEV.INTENCLR.reg = TC_INTENCLR_MC1;
             config[TIMER_1].cb(config[TIMER_1].arg, 1);
         }