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Merge pull request #6838 from aabadie/nucleo32_l432

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boards/nucleo32-l432: initial support
This commit is contained in:
Vincent Dupont 2017-04-13 09:44:05 +02:00 committed by GitHub
commit 70ed63ed25
13 changed files with 15210 additions and 11 deletions
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3
boards/nucleo32-l432/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

1
boards/nucleo32-l432/Makefile.dep Normal file
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@ -0,0 +1 @@
include $(RIOTBOARD)/nucleo-common/Makefile.dep

13
boards/nucleo32-l432/Makefile.features Normal file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo-32 boards
include $(RIOTBOARD)/nucleo32-common/Makefile.features
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_1

6
boards/nucleo32-l432/Makefile.include Normal file
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## the cpu to build for
export CPU = stm32l4
export CPU_MODEL = stm32l432kc
# load the common Makefile.include for Nucleo-32 boards
include $(RIOTBOARD)/nucleo32-common/Makefile.include

36
boards/nucleo32-l432/board.c Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo32-l432
* @{
*
* @file
* @brief Board specific implementations for the nucleo32-l432 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
#ifdef AUTO_INIT_LED0
/* The LED pin is also used for SPI, so we enable it
only if explicitly wanted by the user */
gpio_init(LED0_PIN, GPIO_OUT);
#endif
}

7
boards/nucleo32-l432/dist/openocd.cfg vendored Normal file
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@ -0,0 +1,7 @@
source [find interface/stlink-v2-1.cfg]
transport select hla_swd
source [find target/stm32l4x.cfg]
reset_config srst_only srst_nogate

33
boards/nucleo32-l432/include/board.h Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_nucleo32-l432 Nucleo32-L432
* @ingroup boards
* @brief Board specific files for the nucleo32-l432 board
* @{
*
* @file
* @brief Board specific definitions for the nucleo32-l432 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef BOARD_H
#define BOARD_H
#include "board_common.h"
#ifdef __cplusplus
extern "C" {}
#endif
#endif /* BOARD_H */
/** @} */

205
boards/nucleo32-l432/include/periph_conf.h Normal file
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@ -0,0 +1,205 @@
/*
* Copyright (C) 2017 Inria
* 2017 OTA keys
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo32-l432
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo32-l432 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
#define CLOCK_CORECLOCK (80000000U)
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI @ 48MHz
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [8:86]
* R: post-divider, allowed range: [2,4,6,8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 80MHz MAX!
*/
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (20)
#define CLOCK_PLL_R (2)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR1_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR1_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 15),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF3,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn
},
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_usart1)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name PWM configuration
* @{
*/
static const pwm_conf_t pwm_config[] = {
{
.dev = TIM1,
.rcc_mask = RCC_APB2ENR_TIM1EN,
.chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 },
{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
.af = GPIO_AF1,
.bus = APB2
}
};
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 20000000Hz */
7, /* -> 78125Hz */
5, /* -> 312500Hz */
3, /* -> 1250000Hz */
1, /* -> 5000000Hz */
0 /* -> 10000000Hz */
},
{ /* for APB2 @ 40000000Hz */
7, /* -> 156250Hz */
6, /* -> 312500Hz */
4, /* -> 1250000Hz */
2, /* -> 5000000Hz */
1 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (0U)
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0U)
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (0U)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

10
cpu/stm32l4/include/cpu_conf.h
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@ -1,5 +1,6 @@
/*
* Copyright (C) 2017 Freie Universität Berlin
* 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@ -16,6 +17,7 @@
* @brief Implementation specific CPU configuration options
*
* @author Hauke Petersen <hauke.pertersen@fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef STM32L4_CPU_CONF_H
@ -23,8 +25,10 @@
#include "cpu_conf_common.h"
#ifdef CPU_MODEL_STM32L476RG
#if defined(CPU_MODEL_STM32L476RG)
#include "vendor/stm32l476xx.h"
#elif defined(CPU_MODEL_STM32L432KC)
#include "vendor/stm32l432xx.h"
#endif
#ifdef __cplusplus
@ -36,7 +40,11 @@ extern "C" {
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#if defined(STM32L432KC)
#define CPU_IRQ_NUMOF (82U)
#else
#define CPU_IRQ_NUMOF (81U)
#endif
/** @} */
#ifdef __cplusplus

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cpu/stm32l4/include/vendor/stm32l432xx.h vendored Normal file
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30
cpu/stm32l4/ldscripts/stm32l432kc.ld Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32l4
* @{
*
* @file
* @brief Memory definitions for the STM32L432KC
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1fff7590, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

6
cpu/stm32l4/vectors.c
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@ -111,6 +111,7 @@ WEAK_DEFAULT void isr_lcd(void);
WEAK_DEFAULT void isr_0(void);
WEAK_DEFAULT void isr_rng(void);
WEAK_DEFAULT void isr_fpu(void);
WEAK_DEFAULT void isr_crs(void);
/* interrupt vector table */
ISR_VECTORS const void *interrupt_vector[] = {
@ -216,5 +217,8 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void*) isr_lcd,
(void*) (0UL),
(void*) isr_rng,
(void*) isr_fpu
(void*) isr_fpu,
#if defined(STM32L432KC)
(void*) isr_crs
#endif
};

18
tests/unittests/Makefile
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@ -6,8 +6,8 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon arduino-duemilanove arduino-mega2560 \
cc2650stk chronos ek-lm4f120xl limifrog-v1 maple-mini \
mbed_lpc1768 microbit msb-430 msb-430h nrf51dongle \
nrf6310 nucleo32-f031 nucleo32-f042 nucleo32-f303 \
nucleo32-l031 nucleo-f030 nucleo-f070 nucleo-f072 \
nucleo-f091 nucleo-f103 nucleo-f302 nucleo-f334 \
nucleo32-l031 nucleo32-l432 nucleo-f030 nucleo-f070 \
nucleo-f072 nucleo-f091 nucleo-f103 nucleo-f302 nucleo-f334 \
nucleo-f410 nucleo-l053 nucleo-l073 opencm904 openmote \
openmote-cc2538 pba-d-01-kw2x pca10000 pca10005 \
remote-pa remote-reva remote-revb saml21-xpro \
@ -32,13 +32,13 @@ DISABLE_TEST_FOR_ARM7 := tests-relic tests-cpp_%
ARM_CORTEX_M_BOARDS := airfy-beacon arduino-due arduino-zero cc2538dk ek-lm4f120xl \
f4vi1 fox frdm-k64f iotlab-m3 limifrog-v1 mbed_lpc1768 msbiot \
mulle nrf51dongle nrf52840dk nrf6310 nucleo144-f303 nucleo144-f429 \
nucleo144-f446 nucleo32-f031 nucleo32-f303 nucleo32-l031 nucleo-f030 \
nucleo-f070 nucleo-f072 nucleo-f091 nucleo-f302 nucleo-f303 nucleo-f334 \
nucleo-f401 nucleo-f410 nucleo-f411 nucleo-l053 nucleo-l073 nucleo-l1 \
nucleo-l476 opencm904 openmote-cc2538 pba-d-01-kw2x \
pca10000 pca10005 remote saml21-xpro samr21-xpro slwstk6220a sodaq-autonomo \
spark-core stm32f0discovery stm32f3discovery stm32f4discovery \
udoo weio yunjia-nrf51822
nucleo144-f446 nucleo32-f031 nucleo32-f303 nucleo32-l031 nucleo32-l432 \
nucleo-f030 nucleo-f070 nucleo-f072 nucleo-f091 nucleo-f302 \
nucleo-f303 nucleo-f334 nucleo-f401 nucleo-f410 nucleo-f411 \
nucleo-l053 nucleo-l073 nucleo-l1 nucleo-l476 opencm904 \
openmote-cc2538 pba-d-01-kw2x pca10000 pca10005 remote saml21-xpro \
samr21-xpro slwstk6220a sodaq-autonomo spark-core stm32f0discovery \
stm32f3discovery stm32f4discovery udoo weio yunjia-nrf51822
DISABLE_TEST_FOR_ARM_CORTEX_M := tests-relic