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boards/stm32f4*: use new clock configuration scheme

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This commit is contained in:
Alexandre Abadie 2020-09-04 08:11:58 +02:00
parent 8625e33d78
commit 721625011e
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GPG Key ID: 1C919A403CAE1405
15 changed files with 165 additions and 75 deletions
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10
boards/f4vi1/include/periph_conf.h
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@ -21,8 +21,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 16MHz clock */
#define CLOCK_HSE MHZ(16)
#include "periph_cpu.h"
#include "f4/cfg_clock_168_16_0.h"
#include "f2f4f7/cfg_clock_default_168.h"
#ifdef __cplusplus
extern "C" {

10
boards/msbiot/include/periph_conf.h
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@ -19,8 +19,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 16MHz clock */
#define CLOCK_HSE MHZ(16)
#include "periph_cpu.h"
#include "f4/cfg_clock_168_16_0.h"
#include "f2f4f7/cfg_clock_default_168.h"
#ifdef __cplusplus
extern "C" {

12
boards/nucleo-f401re/include/periph_conf.h
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@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_84_8_1.h"
#include "f2f4f7/cfg_clock_default_84.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f410rb/include/periph_conf.h
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@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_96_8_1.h"
#include "f2f4f7/cfg_clock_default_96.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f411re/include/periph_conf.h
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@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_96_8_1.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f412zg/include/periph_conf.h
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@ -21,8 +21,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_100_8_1.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

12
boards/nucleo-f413zh/include/periph_conf.h
View File

@ -21,8 +21,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_100_8_1.h"
#include "f2f4f7/cfg_clock_default_100.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f429zi/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

12
boards/nucleo-f446re/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"

12
boards/nucleo-f446ze/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
#include "f2f4f7/cfg_clock_default_180.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"

45
boards/pyboard/include/periph_conf.h
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@ -21,44 +21,27 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 12MHz clock */
#define CLOCK_HSE MHZ(12)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (12000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name DMA streams configuration
* @{

12
boards/stm32f429i-disc1/include/periph_conf.h
View File

@ -19,8 +19,18 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_hs_fs.h"

7
boards/stm32f4discovery/include/periph_conf.h
View File

@ -20,8 +20,13 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_0.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus

45
boards/ublox-c030-u201/include/periph_conf.h
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@ -19,44 +19,27 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 12MHz clock */
#define CLOCK_HSE MHZ(12)
#include "periph_cpu.h"
#include "f2f4f7/cfg_clock_default_168.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (12000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name DMA streams configuration
* @{

15
boards/weact-f411ce/include/periph_conf.h
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@ -22,8 +22,21 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides an HSE */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* The HSE provides a 25MHz clock */
#define CLOCK_HSE MHZ(25)
#include "periph_cpu.h"
#include "f4/cfg_clock_96_25_1.h"
#include "f2f4f7/cfg_clock_default_96.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim5.h"
#include "cfg_usb_otg_fs.h"