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sam0: Adapt to flashpage/flashpage_pagewise API

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This commit is contained in:
Koen Zandberg 2020-11-09 16:44:37 +01:00
parent 61052dbed7
commit 72d7a903a2
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GPG Key ID: 0895A893E6D2985B
4 changed files with 8 additions and 23 deletions
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2
cpu/sam0_common/Kconfig
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@ -10,7 +10,7 @@ config CPU_COMMON_SAM0
select HAS_PERIPH_CPUID select HAS_PERIPH_CPUID
select HAS_PERIPH_DMA select HAS_PERIPH_DMA
select HAS_PERIPH_FLASHPAGE select HAS_PERIPH_FLASHPAGE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_FLASHPAGE_RWEE select HAS_PERIPH_FLASHPAGE_RWEE
select HAS_PERIPH_GPIO select HAS_PERIPH_GPIO
select HAS_PERIPH_GPIO_IRQ select HAS_PERIPH_GPIO_IRQ

2
cpu/sam0_common/Makefile.features
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@ -3,7 +3,7 @@ CPU_FAM := $(shell echo $(CPU_MODEL) | cut -c -6)
FEATURES_PROVIDED += periph_cpuid FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_dma
FEATURES_PROVIDED += periph_flashpage FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw FEATURES_PROVIDED += periph_flashpage_pagewise
FEATURES_PROVIDED += periph_flashpage_rwee FEATURES_PROVIDED += periph_flashpage_rwee
FEATURES_PROVIDED += periph_gpio periph_gpio_irq FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_i2c_reconfigure FEATURES_PROVIDED += periph_i2c_reconfigure

4
cpu/sam0_common/include/cpu_conf.h
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@ -111,9 +111,9 @@ as shown in the NVM Row Organization figure. */
/* The minimum block size which can be written is 16B. However, the erase /* The minimum block size which can be written is 16B. However, the erase
* block is always FLASHPAGE_SIZE (SAM0 row). * block is always FLASHPAGE_SIZE (SAM0 row).
*/ */
#define FLASHPAGE_RAW_BLOCKSIZE (16) #define FLASHPAGE_WRITE_BLOCK_SIZE (16)
/* Writing should be always 4 byte aligned */ /* Writing should be always 4 byte aligned */
#define FLASHPAGE_RAW_ALIGNMENT (4) #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4)
/* Add RWWEE memory if supported by revision of the chip /* Add RWWEE memory if supported by revision of the chip
* On some chips it is called RWW EEPROM while on some DATAFLASH, try to * On some chips it is called RWW EEPROM while on some DATAFLASH, try to
* catch all without relying on the CPU model but on the named defines * catch all without relying on the CPU model but on the named defines

23
cpu/sam0_common/periph/flashpage.c
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@ -284,28 +284,13 @@ static void _write_row(uint8_t *dst, const void *_data, size_t len, size_t chunk
} }
} }
void flashpage_write(int page, const void *data) void flashpage_erase(unsigned page)
{ {
assert((unsigned)page < FLASHPAGE_NUMOF); assert((unsigned)page < FLASHPAGE_NUMOF);
_erase_page(flashpage_addr(page), _cmd_erase_row); _erase_page(flashpage_addr(page), _cmd_erase_row);
if (data == NULL) {
return;
} }
/* One RIOT page is FLASHPAGE_PAGES_PER_ROW SAM0 flash pages (a row) as void flashpage_write(void *target_addr, const void *data, size_t len)
* defined in the file cpu/sam0_common/include/cpu_conf.h, therefore we
* have to split the write into FLASHPAGE_PAGES_PER_ROW raw calls
* underneath, each writing a physical page in chunks of 4 bytes (see
* flashpage_write_raw)
* The erasing is done once as a full row is always erased.
*/
_write_row(flashpage_addr(page), data, FLASHPAGE_SIZE, NVMCTRL_PAGE_SIZE,
_cmd_write_page);
}
void flashpage_write_raw(void *target_addr, const void *data, size_t len)
{ {
/* ensure the length doesn't exceed the actual flash size */ /* ensure the length doesn't exceed the actual flash size */
assert(((unsigned)target_addr + len) <= assert(((unsigned)target_addr + len) <=
@ -368,7 +353,7 @@ static void _cmd_write_page_rwwee(void)
#endif #endif
} }
void flashpage_rwwee_write_raw(void *target_addr, const void *data, size_t len) void flashpage_rwwee_write(void *target_addr, const void *data, size_t len)
{ {
assert(((unsigned)target_addr + len) <= assert(((unsigned)target_addr + len) <=
(CPU_FLASH_RWWEE_BASE + (FLASHPAGE_SIZE * FLASHPAGE_RWWEE_NUMOF))); (CPU_FLASH_RWWEE_BASE + (FLASHPAGE_SIZE * FLASHPAGE_RWWEE_NUMOF)));
@ -376,7 +361,7 @@ void flashpage_rwwee_write_raw(void *target_addr, const void *data, size_t len)
_write_row(target_addr, data, len, NVMCTRL_PAGE_SIZE, _cmd_write_page_rwwee); _write_row(target_addr, data, len, NVMCTRL_PAGE_SIZE, _cmd_write_page_rwwee);
} }
void flashpage_rwwee_write(int page, const void *data) void flashpage_rwwee_write_page(unsigned page, const void *data)
{ {
assert((unsigned)page < FLASHPAGE_RWWEE_NUMOF); assert((unsigned)page < FLASHPAGE_RWWEE_NUMOF);