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Merge pull request #15900 from benpicco/cpu/stm32f1-gpio_test_and_clear

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cpu/stm32: GPIO/f1: use bitarithm_test_and_clear()
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benpicco 2021-02-17 15:32:39 +01:00 committed by GitHub
commit 77035d6df3
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1 changed files with 12 additions and 6 deletions
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18
cpu/stm32/periph/gpio_f1.c
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@ -22,6 +22,7 @@
#include "cpu.h" #include "cpu.h"
#include "board.h" #include "board.h"
#include "bitarithm.h"
#include "periph/gpio.h" #include "periph/gpio.h"
#include "periph_cpu.h" #include "periph_cpu.h"
#include "periph_conf.h" #include "periph_conf.h"
@ -40,6 +41,7 @@
* @brief Number of available external interrupt lines * @brief Number of available external interrupt lines
*/ */
#define GPIO_ISR_CHAN_NUMOF (16U) #define GPIO_ISR_CHAN_NUMOF (16U)
#define GPIO_ISR_CHAN_MASK (0xFFFF)
/** /**
* @brief Allocate memory for one callback and argument per EXTI channel * @brief Allocate memory for one callback and argument per EXTI channel
@ -241,12 +243,16 @@ void gpio_irq_disable(gpio_t pin)
void isr_exti(void) void isr_exti(void)
{ {
/* only generate interrupts against lines which have their IMR set */ /* only generate interrupts against lines which have their IMR set */
uint32_t pending_isr = (EXTI->PR & EXTI->IMR); uint32_t pending_isr = (EXTI->PR & EXTI->IMR & GPIO_ISR_CHAN_MASK);
for (unsigned i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
if (pending_isr & (1 << i)) { /* clear by writing a 1 */
EXTI->PR = (1 << i); /* clear by writing a 1 */ EXTI->PR = pending_isr;
exti_ctx[i].cb(exti_ctx[i].arg);
} /* iterate over all set bits */
uint8_t pin = 0;
while (pending_isr) {
pending_isr = bitarithm_test_and_clear(pending_isr, &pin);
exti_ctx[pin].cb(exti_ctx[pin].arg);
} }
cortexm_isr_end(); cortexm_isr_end();
} }