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Merge pull request #15213 from HendrikVE/pr/driver/pca9633-bitarithm

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drivers/pca9633: use bitarithm
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Francisco 2020-11-03 16:00:52 +01:00 committed by GitHub
commit 78bdf7d274
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3 changed files with 63 additions and 62 deletions
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49
drivers/pca9633/include/pca9633_regs.h
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@ -17,6 +17,8 @@
#ifndef PCA9633_REGS_H #ifndef PCA9633_REGS_H
#define PCA9633_REGS_H #define PCA9633_REGS_H
#include "bitarithm.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" extern "C"
{ {
@ -98,47 +100,47 @@ extern "C"
* 0 = disabled * 0 = disabled
* 1 = enabled * 1 = enabled
*/ */
#define PCA9633_BIT_AI2 7 #define PCA9633_BIT_AI2 BIT7
/** /**
* @brief Bit for Auto-Increment bit1 * @brief Bit for Auto-Increment bit1
*/ */
#define PCA9633_BIT_AI1 6 #define PCA9633_BIT_AI1 BIT6
/** /**
* @brief Bit for Auto-Increment bit0 * @brief Bit for Auto-Increment bit0
*/ */
#define PCA9633_BIT_AI0 5 #define PCA9633_BIT_AI0 BIT5
/** /**
* @brief 0 = Normal mode * @brief 0 = Normal mode
* 1 = Low power mode. Oscillator off * 1 = Low power mode. Oscillator off
*/ */
#define PCA9633_BIT_SLEEP 4 #define PCA9633_BIT_SLEEP BIT4
/** /**
* @brief 0 = PCA9633 does not respond to I2C-bus subaddress 1 * @brief 0 = PCA9633 does not respond to I2C-bus subaddress 1
* 1 = PCA9633 responds to I2C-bus subaddress 1 * 1 = PCA9633 responds to I2C-bus subaddress 1
*/ */
#define PCA9633_BIT_SUB1 3 #define PCA9633_BIT_SUB1 BIT3
/** /**
* @brief 0 = PCA9633 does not respond to I2C-bus subaddress 2 * @brief 0 = PCA9633 does not respond to I2C-bus subaddress 2
* 1 = PCA9633 responds to I2C-bus subaddress 2 * 1 = PCA9633 responds to I2C-bus subaddress 2
*/ */
#define PCA9633_BIT_SUB2 2 #define PCA9633_BIT_SUB2 BIT2
/** /**
* @brief 0 = PCA9633 does not respond to I2C-bus subaddress 3 * @brief 0 = PCA9633 does not respond to I2C-bus subaddress 3
* 1 = PCA9633 responds to I2C-bus subaddress 3 * 1 = PCA9633 responds to I2C-bus subaddress 3
*/ */
#define PCA9633_BIT_SUB3 1 #define PCA9633_BIT_SUB3 BIT1
/** /**
* @brief 0 = PCA9633 does not respond to LED All Call I2C-bus address * @brief 0 = PCA9633 does not respond to LED All Call I2C-bus address
* 1 = PCA9633 responds to LED All Call I2C-bus address * 1 = PCA9633 responds to LED All Call I2C-bus address
*/ */
#define PCA9633_BIT_ALLCALL 0 #define PCA9633_BIT_ALLCALL BIT0
@ -147,30 +149,25 @@ extern "C"
/** /**
* @brief Bit for group control; 0=dimming, 1=blinking * @brief Bit for group control; 0=dimming, 1=blinking
*/ */
#define PCA9633_BIT_DMBLNK 5 #define PCA9633_BIT_DMBLNK BIT5
/** /**
* @brief 0 = Output logic state not inverted. Value to use when no external driver used * @brief 0 = Output logic state not inverted. Value to use when no external driver used
* 1 = Output logic state inverted. Value to use when external driver used * 1 = Output logic state inverted. Value to use when external driver used
*/ */
#define PCA9633_BIT_INVRT 4 #define PCA9633_BIT_INVRT BIT4
/** /**
* @brief 0 = Outputs change on STOP command * @brief 0 = Outputs change on STOP command
* 1 = Outputs change on ACK * 1 = Outputs change on ACK
*/ */
#define PCA9633_BIT_OCH 3 #define PCA9633_BIT_OCH BIT3
/** /**
* @brief 0 = The 4 LED outputs are configured with an open-drain structure * @brief 0 = The 4 LED outputs are configured with an open-drain structure
* 1 = The 4 LED outputs are configured with a totem pole structure * 1 = The 4 LED outputs are configured with a totem pole structure
*/ */
#define PCA9633_BIT_OUTDRV 2 #define PCA9633_BIT_OUTDRV BIT2
/**
* @brief See PCA9633_BIT_OUTNE0
*/
#define PCA9633_BIT_OUTNE1 1
/** /**
* @brief 00 = When OE = 1 (output drivers not enabled), LEDn = 0. * @brief 00 = When OE = 1 (output drivers not enabled), LEDn = 0.
@ -180,31 +177,31 @@ extern "C"
* 10 When OE = 1 (output drivers not enabled), LEDn = high-impedance. * 10 When OE = 1 (output drivers not enabled), LEDn = high-impedance.
* 11 reserved * 11 reserved
*/ */
#define PCA9633_BIT_OUTNE0 0 #define PCA9633_BITMASK_OUTNE 0x03
/* Bits in REG_LEDOUT (page 14, table 13) */ /* Bits in REG_LEDOUT (page 14, table 13) */
/** /**
* @brief Lower of two bits for LDR3 * @brief Bitmask for LDR3
*/ */
#define PCA9633_BIT_LDR3 6 #define PCA9633_BITMASK_LDR3 0xC0
/** /**
* @brief Lower of two bits for LDR2 * @brief Bitmask for LDR2
*/ */
#define PCA9633_BIT_LDR2 4 #define PCA9633_BITMASK_LDR2 0x30
/** /**
* @brief Lower of two bits for LDR1 * @brief Bitmask for LDR1
*/ */
#define PCA9633_BIT_LDR1 2 #define PCA9633_BITMASK_LDR1 0x0C
/** /**
* @brief Lower of two bits for LDR0 * @brief Bitmask for LDR0
*/ */
#define PCA9633_BIT_LDR0 0 #define PCA9633_BITMASK_LDR0 0x03
#ifdef __cplusplus #ifdef __cplusplus
} }

68
drivers/pca9633/pca9633.c
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@ -82,7 +82,7 @@ void pca9633_wakeup(pca9633_t* dev)
{ {
uint8_t reg; uint8_t reg;
_read_reg(dev, PCA9633_REG_MODE1, &reg); _read_reg(dev, PCA9633_REG_MODE1, &reg);
reg = reg & ~(1 << PCA9633_BIT_SLEEP); CLRBIT(reg, PCA9633_BIT_SLEEP);
_write_reg(dev, PCA9633_REG_MODE1, reg); _write_reg(dev, PCA9633_REG_MODE1, reg);
} }
@ -91,7 +91,7 @@ void pca9633_sleep(pca9633_t* dev)
{ {
uint8_t reg; uint8_t reg;
_read_reg(dev, PCA9633_REG_MODE1, &reg); _read_reg(dev, PCA9633_REG_MODE1, &reg);
reg = reg | (1 << PCA9633_BIT_SLEEP); SETBIT(reg, PCA9633_BIT_SLEEP);
_write_reg(dev, PCA9633_REG_MODE1, reg); _write_reg(dev, PCA9633_REG_MODE1, reg);
} }
@ -150,19 +150,19 @@ void pca9633_set_rgba(pca9633_t* dev, uint8_t r, uint8_t g, uint8_t b, uint8_t a
void pca9633_set_ldr_state(pca9633_t* dev, void pca9633_set_ldr_state(pca9633_t* dev,
pca9633_ldr_state_t state, pca9633_pwm_channel_t pwm_channel) pca9633_ldr_state_t state, pca9633_pwm_channel_t pwm_channel)
{ {
uint8_t ldr_bit; uint8_t ldr_bitmask;
switch (pwm_channel) { switch (pwm_channel) {
case PCA9633_PWM_CHANNEL_0: case PCA9633_PWM_CHANNEL_0:
ldr_bit = PCA9633_BIT_LDR0; ldr_bitmask = PCA9633_BITMASK_LDR0;
break; break;
case PCA9633_PWM_CHANNEL_1: case PCA9633_PWM_CHANNEL_1:
ldr_bit = PCA9633_BIT_LDR1; ldr_bitmask = PCA9633_BITMASK_LDR1;
break; break;
case PCA9633_PWM_CHANNEL_2: case PCA9633_PWM_CHANNEL_2:
ldr_bit = PCA9633_BIT_LDR2; ldr_bitmask = PCA9633_BITMASK_LDR2;
break; break;
case PCA9633_PWM_CHANNEL_3: case PCA9633_PWM_CHANNEL_3:
ldr_bit = PCA9633_BIT_LDR3; ldr_bitmask = PCA9633_BITMASK_LDR3;
break; break;
default: default:
return; return;
@ -172,60 +172,62 @@ void pca9633_set_ldr_state(pca9633_t* dev,
_read_reg(dev, PCA9633_REG_LEDOUT, &reg); _read_reg(dev, PCA9633_REG_LEDOUT, &reg);
/* first clear both bits of ldr */ /* first clear both bits of ldr */
reg = reg & ~(0b11 << ldr_bit); CLRBIT(reg, ldr_bitmask);
/* second set new state to specified ldr */ /* secondly set new state to specified ldr */
reg |= (state << ldr_bit); SETBIT(reg, (state << bitarithm_lsb(ldr_bitmask)));
_write_reg(dev, PCA9633_REG_LEDOUT, reg); _write_reg(dev, PCA9633_REG_LEDOUT, reg);
} }
void pca9633_set_ldr_state_all(pca9633_t* dev, pca9633_ldr_state_t state) void pca9633_set_ldr_state_all(pca9633_t* dev, pca9633_ldr_state_t state)
{ {
uint8_t reg = (state << PCA9633_BIT_LDR3) uint8_t reg = 0;
| (state << PCA9633_BIT_LDR2)
| (state << PCA9633_BIT_LDR1) SETBIT(reg, (state << bitarithm_lsb(PCA9633_BITMASK_LDR3)));
| (state << PCA9633_BIT_LDR0); SETBIT(reg, (state << bitarithm_lsb(PCA9633_BITMASK_LDR2)));
SETBIT(reg, (state << bitarithm_lsb(PCA9633_BITMASK_LDR1)));
SETBIT(reg, (state << bitarithm_lsb(PCA9633_BITMASK_LDR0)));
_write_reg(dev, PCA9633_REG_LEDOUT, reg); _write_reg(dev, PCA9633_REG_LEDOUT, reg);
} }
void pca9633_set_auto_increment(pca9633_t* dev, pca9633_auto_inc_option_t option) void pca9633_set_auto_increment(pca9633_t* dev, pca9633_auto_inc_option_t option)
{ {
uint8_t new_reg; uint8_t new_reg = 0;
switch (option) { switch (option) {
case PCA9633_AI_ALL: case PCA9633_AI_ALL:
new_reg = (1 << PCA9633_BIT_AI2) SETBIT(new_reg, PCA9633_BIT_AI2);
| (0 << PCA9633_BIT_AI1) CLRBIT(new_reg, PCA9633_BIT_AI1);
| (0 << PCA9633_BIT_AI0); CLRBIT(new_reg, PCA9633_BIT_AI0);
break; break;
case PCA9633_AI_IND: case PCA9633_AI_IND:
new_reg = (1 << PCA9633_BIT_AI2) SETBIT(new_reg, PCA9633_BIT_AI2);
| (1 << PCA9633_BIT_AI1) SETBIT(new_reg, PCA9633_BIT_AI1);
| (0 << PCA9633_BIT_AI0); CLRBIT(new_reg, PCA9633_BIT_AI0);
break; break;
case PCA9633_AI_GBL: case PCA9633_AI_GBL:
new_reg = (1 << PCA9633_BIT_AI2) SETBIT(new_reg, PCA9633_BIT_AI2);
| (0 << PCA9633_BIT_AI1) CLRBIT(new_reg, PCA9633_BIT_AI1);
| (1 << PCA9633_BIT_AI0); SETBIT(new_reg, PCA9633_BIT_AI0);
break; break;
case PCA9633_AI_IND_GBL: case PCA9633_AI_IND_GBL:
new_reg = (1 << PCA9633_BIT_AI2) SETBIT(new_reg, PCA9633_BIT_AI2);
| (1 << PCA9633_BIT_AI1) SETBIT(new_reg, PCA9633_BIT_AI1);
| (1 << PCA9633_BIT_AI0); SETBIT(new_reg, PCA9633_BIT_AI0);
break; break;
case PCA9633_AI_DISABLED: case PCA9633_AI_DISABLED:
/* fall-thru */ /* fall-thru */
default: default:
new_reg = (0 << PCA9633_BIT_AI2) CLRBIT(new_reg, PCA9633_BIT_AI2);
| (0 << PCA9633_BIT_AI1) CLRBIT(new_reg, PCA9633_BIT_AI1);
| (0 << PCA9633_BIT_AI0); CLRBIT(new_reg, PCA9633_BIT_AI0);
break; break;
} }
@ -241,14 +243,16 @@ void pca9633_set_group_control_mode(pca9633_t* dev,
switch (mode) { switch (mode) {
case PCA9633_GROUP_CONTROL_MODE_BLINKING: case PCA9633_GROUP_CONTROL_MODE_BLINKING:
_write_reg(dev, PCA9633_REG_MODE2, prev_reg | (1 << PCA9633_BIT_DMBLNK)); SETBIT(prev_reg, PCA9633_BIT_DMBLNK);
break; break;
case PCA9633_GROUP_CONTROL_MODE_DIMMING: case PCA9633_GROUP_CONTROL_MODE_DIMMING:
default: default:
_write_reg(dev, PCA9633_REG_MODE2, prev_reg & ~(1 << PCA9633_BIT_DMBLNK)); CLRBIT(prev_reg, PCA9633_BIT_DMBLNK);
break; break;
} }
_write_reg(dev, PCA9633_REG_MODE2, prev_reg);
} }
int _write_reg(pca9633_t* dev, uint8_t reg, uint8_t data) int _write_reg(pca9633_t* dev, uint8_t reg, uint8_t data)

8
tests/driver_pca9633/main.c
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@ -399,25 +399,25 @@ int run_demo(int argc, char **argv)
puts("4. changing ldr state"); puts("4. changing ldr state");
pca9633_set_grp_pwm(&pca9633_dev, 255); pca9633_set_grp_pwm(&pca9633_dev, 255);
pca9633_set_rgb(&pca9633_dev, 255, 255, 255); pca9633_set_rgb(&pca9633_dev, 255, 255, 255);
pca9633_set_ldr_state(&pca9633_dev, PCA9633_LDR_STATE_OFF, PCA9633_BIT_LDR1); pca9633_set_ldr_state(&pca9633_dev, PCA9633_LDR_STATE_OFF, PCA9633_PWM_CHANNEL_1);
// color should be magenta // color should be magenta
xtimer_usleep(500 * US_PER_MS); xtimer_usleep(500 * US_PER_MS);
pca9633_set_grp_pwm(&pca9633_dev, 0); pca9633_set_grp_pwm(&pca9633_dev, 0);
pca9633_set_rgb(&pca9633_dev, 0, 0, 0); pca9633_set_rgb(&pca9633_dev, 0, 0, 0);
pca9633_set_ldr_state(&pca9633_dev, PCA9633_LDR_STATE_ON, PCA9633_BIT_LDR1); pca9633_set_ldr_state(&pca9633_dev, PCA9633_LDR_STATE_ON, PCA9633_PWM_CHANNEL_1);
// color should be green // color should be green
xtimer_usleep(500 * US_PER_MS); xtimer_usleep(500 * US_PER_MS);
pca9633_set_grp_pwm(&pca9633_dev, 255); pca9633_set_grp_pwm(&pca9633_dev, 255);
pca9633_set_rgb(&pca9633_dev, 255, 128, 0); pca9633_set_rgb(&pca9633_dev, 255, 128, 0);
pca9633_set_ldr_state(&pca9633_dev,PCA9633_LDR_STATE_IND, PCA9633_BIT_LDR1); pca9633_set_ldr_state(&pca9633_dev,PCA9633_LDR_STATE_IND, PCA9633_PWM_CHANNEL_1);
// color should be orange // color should be orange
xtimer_usleep(500 * US_PER_MS); xtimer_usleep(500 * US_PER_MS);
pca9633_set_grp_pwm(&pca9633_dev, 0); pca9633_set_grp_pwm(&pca9633_dev, 0);
pca9633_set_rgb(&pca9633_dev, 255, 255, 255); pca9633_set_rgb(&pca9633_dev, 255, 255, 255);
pca9633_set_ldr_state(&pca9633_dev, PCA9633_LDR_STATE_IND_GRP, PCA9633_BIT_LDR1); pca9633_set_ldr_state(&pca9633_dev, PCA9633_LDR_STATE_IND_GRP, PCA9633_PWM_CHANNEL_1);
// should be no color at all // should be no color at all
xtimer_usleep(500 * US_PER_MS); xtimer_usleep(500 * US_PER_MS);