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samd21/cpu:waitstates for low voltage

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This commit is contained in:
Dan Evans 2017-05-01 12:04:31 -06:00
parent f5a4124866
commit 7a8551574b
1 changed files with 20 additions and 4 deletions
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24
cpu/samd21/cpu.c
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@ -22,6 +22,24 @@
#include "periph_conf.h" #include "periph_conf.h"
#include "periph/init.h" #include "periph/init.h"
#ifndef VDD
/**
* @brief Set system voltage level in mV (determines flash wait states)
*
* @note Override this value in your boards periph_conf.h file
* if a different system voltage is used.
*/
#define VDD (3300U)
#endif
/* determine the needed flash wait states based on the system voltage (Vdd)
* see SAMD21 datasheet Rev A (2017) table 37-40 , page 816 */
#if (VDD > 2700)
#define WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000)
#else
#define WAITSTATES ((CLOCK_CORECLOCK - 1) / 14000000)
#endif
/** /**
* @brief Configure clock sources and the cpu frequency * @brief Configure clock sources and the cpu frequency
*/ */
@ -31,12 +49,10 @@ static void clk_init(void)
PM->APBAMASK.reg = (PM_APBAMASK_PM | PM_APBAMASK_SYSCTRL | PM->APBAMASK.reg = (PM_APBAMASK_PM | PM_APBAMASK_SYSCTRL |
PM_APBAMASK_GCLK); PM_APBAMASK_GCLK);
/* adjust NVM wait states, see table 42.30 (p. 1070) in the datasheet */ /* adjust NVM wait states */
#if (CLOCK_CORECLOCK > 24000000)
PM->APBBMASK.reg |= PM_APBBMASK_NVMCTRL; PM->APBBMASK.reg |= PM_APBBMASK_NVMCTRL;
NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1); NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(WAITSTATES);
PM->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL; PM->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL;
#endif
/* configure internal 8MHz oscillator to run without prescaler */ /* configure internal 8MHz oscillator to run without prescaler */
SYSCTRL->OSC8M.bit.PRESC = 0; SYSCTRL->OSC8M.bit.PRESC = 0;