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cpu/stm32l5: adapt flashpage periph

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This commit is contained in:
Alexandre Abadie 2020-09-28 15:58:30 +02:00
parent a416b2793f
commit 7f26d5c389
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GPG Key ID: 1C919A403CAE1405
4 changed files with 43 additions and 14 deletions
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2
cpu/stm32/Makefile.features
View File

@ -9,7 +9,7 @@ FEATURES_PROVIDED += periph_uart_modecfg
FEATURES_PROVIDED += periph_uart_nonblocking
FEATURES_PROVIDED += periph_wdt
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 wb))
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb))
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
endif

5
cpu/stm32/include/cpu_conf.h
View File

@ -89,12 +89,13 @@ extern "C" {
* @brief Flash page configuration
* @{
*/
#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32L5)
#if defined(CPU_FAM_STM32WB)
#define FLASHPAGE_SIZE (4096U)
#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
|| defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
|| defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0)
|| defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
|| defined(CPU_FAM_STM32L5)
#define FLASHPAGE_SIZE (2048U)
#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
|| defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \

20
cpu/stm32/periph/flash_common.c
View File

@ -31,6 +31,13 @@
#define CNTRL_REG (FLASH->PECR)
#define CNTRL_REG_LOCK (FLASH_PECR_PELOCK)
#define KEY_REG (FLASH->PEKEYR)
#elif defined(CPU_FAM_STM32L5)
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define CNTRL_REG (FLASH->NSCR)
#define CNTRL_REG_LOCK (FLASH_NSCR_NSLOCK)
#define KEY_REG (FLASH->NSKEYR)
#define FLASH_SR_EOP (FLASH_NSSR_NSEOP)
#else
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0)
@ -46,6 +53,13 @@
#define FLASH_SR_BSY (FLASH_SR_BSY1)
#endif
#if defined(CPU_FAM_STM32L5)
#define FLASH_SR_BSY (FLASH_NSSR_NSBSY)
#define FLASH_SR_REG (FLASH->NSSR)
#else
#define FLASH_SR_REG (FLASH->SR)
#endif
void _unlock(void)
{
if (CNTRL_REG & CNTRL_REG_LOCK) {
@ -65,9 +79,9 @@ void _lock(void)
void _wait_for_pending_operations(void)
{
if (FLASH->SR & FLASH_SR_BSY) {
if (FLASH_SR_REG & FLASH_SR_BSY) {
DEBUG("[flash-common] waiting for any pending operation to finish\n");
while (FLASH->SR & FLASH_SR_BSY) {}
while (FLASH_SR_REG & FLASH_SR_BSY) {}
}
/* Clear 'end of operation' bit in status register, for other STM32 boards
@ -75,6 +89,6 @@ void _wait_for_pending_operations(void)
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L1)
FLASH->SR |= FLASH_SR_EOP;
FLASH_SR_REG |= FLASH_SR_EOP;
#endif
}

30
cpu/stm32/periph/flashpage.c
View File

@ -39,9 +39,20 @@
#define CNTRL_REG_LOCK (FLASH_PECR_PELOCK)
#define FLASH_CR_PER (FLASH_PECR_ERASE | FLASH_PECR_PROG)
#define FLASHPAGE_DIV (4U) /* write 4 bytes in one go */
#elif defined(CPU_FAM_STM32L5)
#define FLASHPAGE_DIV (8U)
#define CNTRL_REG (FLASH->NSCR)
#define CNTRL_REG_LOCK (FLASH_NSCR_NSLOCK)
#define FLASH_CR_PNB (FLASH_NSCR_NSPNB)
#define FLASH_CR_PNB_Pos (FLASH_NSCR_NSPNB_Pos)
#define FLASH_CR_STRT (FLASH_NSCR_NSSTRT)
#define FLASH_CR_PER (FLASH_NSCR_NSPER)
#define FLASH_CR_BKER (FLASH_NSCR_NSBKER)
#define FLASH_CR_PG (FLASH_NSCR_NSPG)
#else
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
#define FLASHPAGE_DIV (8U)
#else
#define FLASHPAGE_DIV (2U)
@ -54,7 +65,7 @@ extern void _lock(void);
extern void _unlock(void);
extern void _wait_for_pending_operations(void);
#if defined(CPU_FAM_STM32G4)
#if defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
#define MAX_PAGES_PER_BANK (128)
#else /* CPU_FAM_STM32L4 */
#define MAX_PAGES_PER_BANK (256)
@ -80,7 +91,8 @@ static void _erase_page(void *page_addr)
{
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
uint32_t *dst = page_addr;
#else
uint16_t *dst = page_addr;
@ -106,7 +118,8 @@ static void _erase_page(void *page_addr)
DEBUG("[flashpage] erase: trigger the page erase\n");
*dst = (uint32_t)0;
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
DEBUG("[flashpage] erase: setting the page address\n");
uint8_t pn;
#if (FLASHPAGE_NUMOF <= MAX_PAGES_PER_BANK) || defined(CPU_FAM_STM32WB)
@ -168,7 +181,8 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
uint32_t *dst = target_addr;
const uint32_t *data_addr = data;
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
defined(CPU_FAM_STM32L5)
uint64_t *dst = target_addr;
const uint64_t *data_addr = data;
#else
@ -193,7 +207,7 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5)
/* set PG bit and program page to flash */
CNTRL_REG |= FLASH_CR_PG;
#endif
@ -208,7 +222,7 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5)
CNTRL_REG &= ~(FLASH_CR_PG);
#endif
DEBUG("[flashpage_raw] write: done writing data\n");
@ -238,7 +252,7 @@ void flashpage_write(int page, const void *data)
/* STM32L0/L1 only supports word sizes */
uint32_t *page_addr = flashpage_addr(page);
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \
defined(CPU_FAM_STM32G0)
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5)
uint64_t *page_addr = flashpage_addr(page);
#else
/* Default is to support half-word sizes */