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Merge pull request #4681 from haukepetersen/opt_f1_cpuheaders

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cpu/stm32f1: udpated vendor headers
This commit is contained in:
Martine Lenders 2016-01-27 03:53:37 +01:00
commit 80023f07d8
9 changed files with 8537 additions and 4080 deletions
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2
boards/fox/include/periph_conf.h
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@ -31,7 +31,7 @@ extern "C" {
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_Div2
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_DIV2
#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */

2
boards/iotlab-m3/include/periph_conf.h
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@ -32,7 +32,7 @@ extern "C" {
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_Div2
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_DIV2
#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */

21
boards/spark-core/include/periph_conf.h
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@ -27,11 +27,11 @@
* @name Clock system configuration
* @{
**/
#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
#define CLOCK_HSE (8000000U) /* frequency of external oscillator */
#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE
#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE /* not divided */
#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
@ -45,9 +45,8 @@
* @brief Timer configuration
* @{
*/
#define TIMER_NUMOF (2U)
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
#define TIMER_1_EN 1
/* Timer 0 configuration */
#define TIMER_0_DEV_0 TIM2
@ -62,20 +61,6 @@
#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
#define TIMER_0_IRQ_PRIO 1
#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
/* Timer 1 configuration */
#define TIMER_1_DEV_0 TIM4
#define TIMER_1_DEV_1 TIM5
#define TIMER_1_CHANNELS 4
#define TIMER_1_PRESCALER (36000U)
#define TIMER_1_MAX_VALUE (0xffff)
#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
#define TIMER_1_ISR_0 isr_tim4
#define TIMER_1_ISR_1 isr_tim5
#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
#define TIMER_1_IRQ_PRIO 1
#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
/** @} */
/**

128
boards/spark-core/system_stm32f1.c
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@ -1,128 +0,0 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_spark-core
* @{
*
* @file
* @brief Board specific clock setup
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
#include "stm32f10x.h"
#include "board.h"
uint32_t SystemCoreClock = F_CPU;
#define VECT_TAB_OFFSET 0x0
static void set_system_clock(void)
{
volatile uint32_t startup_counter = 0, HSE_status = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do {
HSE_status = RCC->CR & RCC_CR_HSERDY;
startup_counter++;
}
while ((HSE_status == 0) && (startup_counter != HSE_STARTUP_TIMEOUT));
if (!(RCC->CR & RCC_CR_HSERDY)) {
HSE_status = (uint32_t)0x01;
}
else {
HSE_status = (uint32_t)0x00;
}
if (HSE_status == (uint32_t)0x01) {
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
/* NOTE : agilefox : modified to take into account the 16MHz
crystal instead of 8MHz */
/* PLL configuration: PLLCLK = HSE / 2 * 9 = 72 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC
| RCC_CFGR_PLLXTPRE
| RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE
| RCC_CFGR_PLLXTPRE_HSE_Div2
| RCC_CFGR_PLLMULL9);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while ((RCC->CR & RCC_CR_PLLRDY) == 0) {
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) {
}
}
else {
/* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
RCC->CFGR &= (uint32_t)0xF0FF0000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
set_system_clock();
/* Vector Table Relocation in Internal FLASH. */
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
}

2
cpu/stm32f1/cpu.c
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@ -74,7 +74,7 @@ static void clk_init(void)
RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
/* PLL configuration: PLLCLK = HSE / HSE_DIV * HSE_MUL */
RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL);
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */

12
cpu/stm32f1/include/cpu_conf.h
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@ -20,10 +20,14 @@
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef __CPU_CONF_H
#define __CPU_CONF_H
#ifndef CPU_CONF_H
#define CPU_CONF_H
#include "stm32f10x.h"
#if defined(CPU_MODEL_STM32F103CB) || defined(CPU_MODEL_STM32F103RB)
#include "stm32f103xb.h"
#elif defined(CPU_MODEL_STM32F103RE)
#include "stm32f103xe.h"
#endif
#ifdef __cplusplus
extern "C" {
@ -56,5 +60,5 @@ void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t *prescale);
}
#endif
#endif /* __CPU_CONF_H */
#endif /* CPU_CONF_H */
/** @} */

6047
cpu/stm32f1/include/stm32f103xb.h Normal file
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File diff suppressed because it is too large Load Diff

6401
cpu/stm32f1/include/stm32f10x.h → cpu/stm32f1/include/stm32f103xe.h
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File diff suppressed because it is too large Load Diff

2
cpu/stm32f1/periph/spi.c
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@ -21,7 +21,7 @@
* @}
*/
#include "stm32f10x.h"
#include "cpu.h"
#include "mutex.h"
#include "periph/gpio.h"
#include "periph/spi.h"