cpu/qn908x: Add missing gpio & uart enum values.

GPIO_BOTH gpio_flank_t; UART_PARTY_MARK and UART_PARTY_SPACE in
uart_parity_t; and UART_DATA_BITS_5 and UART_DATA_BITS_6
uart_data_bits_t enum values where missing from the periph_cpu.h header
since they are not supported by the CPU. This was causing some tests to
fail to compile, but only after adding the periph_timer module.

This patch adds those missing macros and makes the corresponding
functions fail when trying to use them.

A minor fix to the NWDT_TIME_LOWER_LIMIT value setting it to 1U to avoid
a -Werror=type-limits error in the tests/periph_wdt test. In theory 0
is a totally valid value although a bit useless since it will trigger
the WDT right away.

cpu/qn908x/include/periph_cpu.h

@@ -81,9 +81,9 @@ typedef uint16_t gpio_t;
  * clocks installed on the board. Figure out a way to configure this limit based
  * on the clock used.
  */
-#define NWDT_TIME_LOWER_LIMIT (0)
+#define NWDT_TIME_LOWER_LIMIT (1U)
 #define NWDT_TIME_UPPER_LIMIT (268435U)
-#define WWDT_TIME_LOWER_LIMIT (0)
+#define WWDT_TIME_LOWER_LIMIT (1U)
 #define WWDT_TIME_UPPER_LIMIT (268435U)
 /** @} */
 
@@ -127,6 +127,7 @@ typedef enum {
     GPIO_HIGH       = 1,    /**< emit interrupt when the value is high */
     GPIO_RISING     = 2,    /**< emit interrupt on rising flank */
     GPIO_FALLING    = 3,    /**< emit interrupt on falling flank */
+    GPIO_BOTH       = 4,    /**< not supported -- rising and falling flanks */
 } gpio_flank_t;
 /** @} */
 #endif /* ndef DOXYGEN */
@@ -153,6 +154,13 @@ typedef struct {
     gpio_t tx_pin;      /**< TX pin, GPIO_UNDEF disables TX. */
 } uart_conf_t;
 
+/**
+ * @brief   Invalid UART mode mask
+ *
+ * Signals that the mode is invalid or not supported by the CPU.
+ */
+#define UART_INVALID_MODE   (0x80)
+
 /**
  * @brief   Definition of possible parity modes
  *
@@ -164,6 +172,8 @@ typedef enum {
     UART_PARITY_NONE = 0,                         /**< no parity */
     UART_PARITY_EVEN = 2,                         /**< even parity */
     UART_PARITY_ODD = 3,                          /**< odd parity */
+    UART_PARITY_MARK = 0x10 | UART_INVALID_MODE,  /**< mark parity */
+    UART_PARITY_SPACE = 0x20 | UART_INVALID_MODE, /**< space parity */
 } uart_parity_t;
 #define HAVE_UART_PARITY_T
 /** @} */
@@ -175,6 +185,8 @@ typedef enum {
  * @{
  */
 typedef enum {
+    UART_DATA_BITS_5 = 0x10 | UART_INVALID_MODE, /**< 5 data bits */
+    UART_DATA_BITS_6 = 0x20 | UART_INVALID_MODE, /**< 6 data bits */
     UART_DATA_BITS_7 = 0,                        /**< 7 data bits */
     UART_DATA_BITS_8 = 1,                        /**< 8 data bits */
     /* Note: There's a UART_DATA_BITS_9 possible in this hardware. */

cpu/qn908x/periph/gpio.c

@@ -122,6 +122,10 @@ static gpio_isr_cb_state_t gpio_isr_state[TOTAL_GPIO_PINS] = {};
 int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
                   gpio_cb_t cb, void *arg)
 {
+    if (flank == GPIO_BOTH) {
+        /* GPIO_BOTH is not supported. */
+        return -1;
+    }
     uint8_t gpio_num = GPIO_T_PORT(pin) * PINS_PER_PORT + GPIO_T_PIN(pin);
 
     if (gpio_num >= TOTAL_GPIO_PINS) {
@@ -154,6 +158,9 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
             base->INTTYPESET = mask;    /* SET = edge */
             base->INTPOLSET = mask;     /* SET = rising */
             break;
+        case GPIO_BOTH:
+            /* Handled above */
+            break;
     }
     gpio_irq_enable(pin);
     return 0;

cpu/qn908x/periph/uart.c

@@ -223,6 +223,9 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
 int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
               uart_stop_bits_t stop_bits)
 {
+    if ((data_bits & UART_INVALID_MODE) || (parity & UART_INVALID_MODE)) {
+        return UART_NOMODE;
+    }
     /* Setup mode and enable USART. The values of the uart_data_bits_t,
      * uart_parity_t and uart_stop_bits_t enums were selected to match the
      * fields in this registers so there's no need to do any conversion. */