diff --git a/cpu/saml1x/cpu.c b/cpu/saml1x/cpu.c
index f3ee82c2eb..1234865ad3 100644
--- a/cpu/saml1x/cpu.c
+++ b/cpu/saml1x/cpu.c
@@ -22,6 +22,12 @@
 #include "periph/init.h"
 #include "board.h"
 
+#ifdef CPU_FAM_SAML11
+#define _NVMCTRL NVMCTRL_SEC
+#else
+#define _NVMCTRL NVMCTRL
+#endif
+
 static void _gclk_setup(int gclk, uint32_t reg)
 {
     GCLK->GENCTRL[gclk].reg = reg;
@@ -40,6 +46,7 @@ void cpu_init(void)
     MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK
                          | MCLK_APBAMASK_OSCCTRL
                          | MCLK_APBAMASK_GCLK
+                         | MCLK_APBAMASK_PM
 #ifdef MODULE_PERIPH_GPIO_IRQ
                          | MCLK_APBAMASK_EIC
 #endif
@@ -53,6 +60,13 @@ void cpu_init(void)
     while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
     while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
 
+    PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
+    while (0 == PM->INTFLAG.bit.PLRDY) {}
+
+    MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
+    _NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1);
+    MCLK->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
+
     /* set OSC16M to 16MHz */
     OSCCTRL->OSC16MCTRL.bit.FSEL = 3;
     OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
@@ -61,11 +75,6 @@ void cpu_init(void)
     /* Setup GCLK generators */
     _gclk_setup(0, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
 
-#ifdef MODULE_PERIPH_PM
-    /* enable power managemet module */
-    MCLK->APBAMASK.reg |= MCLK_APBAMASK_PM;
-#endif
-
     /* trigger static peripheral initialization */
     periph_init();
 }