From 84bbee784deaaf8fbb300f2d3d5e5e601e99572d Mon Sep 17 00:00:00 2001
From: Alexandre Abadie <alexandre.abadie@inria.fr>
Date: Mon, 24 Aug 2020 14:06:15 +0200
Subject: [PATCH] cpu/stm32: add transition phase when raising +80MHz clock

---
 cpu/stm32/stmclk/stmclk_gx.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/cpu/stm32/stmclk/stmclk_gx.c b/cpu/stm32/stmclk/stmclk_gx.c
index 30e6e257da..396e53615f 100644
--- a/cpu/stm32/stmclk/stmclk_gx.c
+++ b/cpu/stm32/stmclk/stmclk_gx.c
@@ -155,9 +155,23 @@ void stmclk_init_sysclk(void)
     RCC->CR |= RCC_CR_PLLON;
     while (!(RCC->CR & RCC_CR_PLLRDY)) {}
 
+#if CLOCK_AHB > MHZ(80)
+    /* Divide HCLK by before enabling the PLL */
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV2;
+#endif
+
     /* now that the PLL is running, we use it as system clock */
     RCC->CFGR |= RCC_CFGR_SW_PLL;
     while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
+
+#if CLOCK_AHB > MHZ(80)
+    /* Wait 1us before switching back to full speed */
+    /* Use volatile to prevent the compiler from optimizing the loop */
+    volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1);
+    while (count--) {}
+    RCC->CFGR &= ~RCC_CFGR_HPRE_DIV2;
+#endif
+
 #endif
 
     stmclk_disable_hsi();