riot-ci/RIOT
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

boards/nucleo-f401: adapted to UART driver update

Browse Source
This commit is contained in:
Hauke Petersen 2015-12-01 14:44:37 +01:00
parent b75e5fe407
commit 84fd4d7a5a
2 changed files with 26 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
boards/nucleo-f401/include/board.h
View File

@ -47,7 +47,7 @@ extern "C" {
* @name Define UART device and baudrate for stdio * @name Define UART device and baudrate for stdio
* @{ * @{
*/ */
#define STDIO UART_0 #define STDIO UART_DEV(0)
#define STDIO_BAUDRATE (115200U) #define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U) #define STDIO_RX_BUFSIZE (64U)
/** @} */ /** @} */

41
boards/nucleo-f401/include/periph_conf.h
View File

@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_ #ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_ #define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
@ -39,6 +41,11 @@ extern "C" {
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/** @} */ /** @} */
/** /**
@ -73,24 +80,26 @@ extern "C" {
* @name UART configuration * @name UART configuration
* @{ * @{
*/ */
#define UART_NUMOF (1U) static const uart_conf_t uart_config[] = {
#define UART_0_EN 1 /* device, RCC mask, RX pin, TX pin, pin AF, IRQ channel, DMA stream, DMA */
#define UART_IRQ_PRIO 1 {
#define UART_CLK (14000000U) /* UART clock runs with 14MHz */ USART2, /* device base register */
RCC_APB1ENR_USART2EN, /* RCC mask */
GPIO_PIN(PORT_A,3), /* RX pin */
GPIO_PIN(PORT_A,2), /* TX pin */
GPIO_AF7, /* pin AF */
USART2_IRQn, /* IRQ channel */
6, /* DMA stream */
4 /* DMA channel */
}
};
/* UART 0 device configuration */ /* assign ISR vector names */
#define UART_0_DEV USART2
#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
#define UART_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define UART_0_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 42MHz (F_CPU / 2) */
#define UART_0_IRQ_CHAN USART2_IRQn
#define UART_0_ISR isr_usart2 #define UART_0_ISR isr_usart2
/* UART 0 pin configuration */ #define UART_0_DMA_ISR isr_dma1_stream6
#define UART_0_PORT GPIOA
#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) /* deduct number of defined UART interfaces */
#define UART_0_RX_PIN 3 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
#define UART_0_TX_PIN 2
#define UART_0_AF 7
/** @} */ /** @} */
/** /**