From 8a9d9e70bc9e47cffd41b0ac0a76d3c7f5fb8267 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Mon, 7 Jan 2019 16:01:59 +0100 Subject: [PATCH] cpu/stm32f2: update CMSIS of stm32f207xx --- cpu/stm32f2/include/vendor/stm32f207xx.h | 16403 +++++++++++++++------ 1 file changed, 11544 insertions(+), 4859 deletions(-) diff --git a/cpu/stm32f2/include/vendor/stm32f207xx.h b/cpu/stm32f2/include/vendor/stm32f207xx.h index 0c013424e1..13b591fcee 100644 --- a/cpu/stm32f2/include/vendor/stm32f207xx.h +++ b/cpu/stm32f2/include/vendor/stm32f207xx.h @@ -2,18 +2,16 @@ ****************************************************************************** * @file stm32f207xx.h * @author MCD Application Team - * @version V2.1.2 - * @date 29-June-2016 * @brief CMSIS STM32F207xx Device Peripheral Access Layer Header File. * This file contains : * - Data structures and the address mapping for all peripherals * - Peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral�s registers hardware * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -84,6 +82,7 @@ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ @@ -171,7 +170,7 @@ typedef enum OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ - HASH_RNG_IRQn = 80 /*!< Hash and RNG global interrupt */ + HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ } IRQn_Type; /** @@ -392,7 +391,8 @@ typedef struct uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; @@ -753,7 +753,7 @@ typedef struct __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR[4]; /*!< TIM capture/compare register 1-4, Address offset: 0x34 */ + __IO uint32_t CCR[4]; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ @@ -786,7 +786,6 @@ typedef struct __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; - /** * @brief RNG */ @@ -936,6 +935,8 @@ USB_OTG_HostChannelTypeDef; #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ #define FLASH_END 0x080FFFFFU /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE @@ -983,7 +984,10 @@ USB_OTG_HostChannelTypeDef; #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) +#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U) +/* Legacy define */ +#define ADC_BASE ADC123_COMMON_BASE + #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) @@ -1059,6 +1063,10 @@ USB_OTG_HostChannelTypeDef; #define USB_OTG_FIFO_BASE 0x1000U #define USB_OTG_FIFO_SIZE 0x1000U +/******************* Device electronic signature ***************/ +#define UID_BASE 0x1FFF7A10 /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FFF7A22 /*!< FLASH Size register base address */ + /** * @} */ @@ -1090,15 +1098,18 @@ USB_OTG_HostChannelTypeDef; #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) +/* Legacy define */ +#define ADC ADC123_COMMON #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) @@ -1171,365 +1182,593 @@ USB_OTG_HostChannelTypeDef; /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD 0x00000001U /*!