From 8ac1909ea3baf0cfffcec072d6ebb0994dfa276b Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 4 Sep 2020 09:17:40 +0200 Subject: [PATCH] cpu: boards: stm32l0l1: use IS_ACTIVE where possible in stmclk --- boards/b-l072z-lrwan1/include/periph_conf.h | 2 +- .../stm32/include/l0l1/cfg_clock_default.h | 79 ++++++++++--------- boards/i-nucleo-lrwan1/include/periph_conf.h | 2 +- boards/im880b/include/periph_conf.h | 2 +- boards/lobaro-lorabox/include/periph_conf.h | 2 +- boards/lsn50/include/periph_conf.h | 2 +- boards/nucleo-l031k6/include/periph_conf.h | 2 +- boards/nucleo-l053r8/include/periph_conf.h | 2 +- boards/nucleo-l073rz/include/periph_conf.h | 2 +- cpu/stm32/stmclk/stmclk_l0l1.c | 23 +++--- 10 files changed, 60 insertions(+), 58 deletions(-) diff --git a/boards/b-l072z-lrwan1/include/periph_conf.h b/boards/b-l072z-lrwan1/include/periph_conf.h index d618bce0b4..3381fb6bd7 100644 --- a/boards/b-l072z-lrwan1/include/periph_conf.h +++ b/boards/b-l072z-lrwan1/include/periph_conf.h @@ -21,7 +21,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/common/stm32/include/l0l1/cfg_clock_default.h b/boards/common/stm32/include/l0l1/cfg_clock_default.h index a50a4e6858..883a70e8f3 100644 --- a/boards/common/stm32/include/l0l1/cfg_clock_default.h +++ b/boards/common/stm32/include/l0l1/cfg_clock_default.h @@ -33,63 +33,63 @@ extern "C" { #ifndef CONFIG_USE_CLOCK_PLL #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \ IS_ACTIVE(CONFIG_USE_CLOCK_MSI) -#define CONFIG_USE_CLOCK_PLL (0) +#define CONFIG_USE_CLOCK_PLL 0 #else -#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */ +#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */ #endif #endif /* CONFIG_USE_CLOCK_PLL */ #ifndef CONFIG_USE_CLOCK_MSI -#define CONFIG_USE_CLOCK_MSI (0) +#define CONFIG_USE_CLOCK_MSI 0 #endif /* CONFIG_USE_CLOCK_MSI */ #ifndef CONFIG_USE_CLOCK_HSE -#define CONFIG_USE_CLOCK_HSE (0) +#define CONFIG_USE_CLOCK_HSE 0 #endif /* CONFIG_USE_CLOCK_HSE */ #ifndef CONFIG_USE_CLOCK_HSI -#define CONFIG_USE_CLOCK_HSI (0) +#define CONFIG_USE_CLOCK_HSI 0 #endif /* CONFIG_USE_CLOCK_HSI */ -#if CONFIG_USE_CLOCK_PLL && \ - (CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use PLL as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_MSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use MSI as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSE && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use HSE as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \ + IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) #error "Cannot use HSI as clock source with other clock configurations" #endif #ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE (0) +#define CONFIG_BOARD_HAS_HSE 0 #endif #ifndef CLOCK_HSE #define CLOCK_HSE MHZ(24) #endif -#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24)) #error "HSE clock frequency must be between 1MHz and 24MHz" #endif -#ifndef CONFIG_CLOCK_HSI_USE_DIV4 -#define CONFIG_CLOCK_HSI_USE_DIV4 (0) -#endif - #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (0) +#define CONFIG_BOARD_HAS_LSE 0 #endif -#if CONFIG_BOARD_HAS_LSE +#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE) #define CLOCK_LSE (1) #else #define CLOCK_LSE (0) @@ -101,27 +101,28 @@ extern "C" { #define CONFIG_CLOCK_MSI KHZ(4194) #endif -#if CONFIG_USE_CLOCK_HSI -#define CLOCK_CORECLOCK (CLOCK_HSI) - -#elif CONFIG_USE_CLOCK_HSE -#if CONFIG_BOARD_HAS_HSE == 0 -#error "The board doesn't provide an HSE oscillator" -#endif -#define CLOCK_CORECLOCK (CLOCK_HSE) - -#elif CONFIG_USE_CLOCK_MSI -#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) - -#elif CONFIG_USE_CLOCK_PLL -/* The following parameters configure a 64MHz system clock with HSI as input clock */ +/* The following parameters configure a 32MHz system clock with HSI as input clock */ #ifndef CONFIG_CLOCK_PLL_DIV #define CONFIG_CLOCK_PLL_DIV (2) #endif #ifndef CONFIG_CLOCK_PLL_MUL #define CONFIG_CLOCK_PLL_MUL (4) #endif -#if CONFIG_BOARD_HAS_HSE + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CLOCK_CORECLOCK (CLOCK_HSI) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) +#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#error "The board doesn't provide an HSE oscillator" +#endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI) +#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #if CLOCK_HSE < MHZ(2) #error "HSE must be greater than 2MHz when used as PLL input clock" #endif @@ -134,9 +135,9 @@ extern "C" { * compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL) * with: * PLL_IN: input clock is HSE if available or HSI otherwise - * PLL_DIV : divider, allowed values: 2, 3, 4 - * PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48 - * CORECLOCK -> 48MHz MAX! + * PLL_DIV : divider, allowed values: 2, 3, 4. Default is 2. + * PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48. Default is 4. + * CORECLOCK -> 32MHz MAX! */ #define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL) #if CLOCK_CORECLOCK > MHZ(32) diff --git a/boards/i-nucleo-lrwan1/include/periph_conf.h b/boards/i-nucleo-lrwan1/include/periph_conf.h index 6ee600b59d..f97514f0f7 100644 --- a/boards/i-nucleo-lrwan1/include/periph_conf.h +++ b/boards/i-nucleo-lrwan1/include/periph_conf.h @@ -21,7 +21,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/im880b/include/periph_conf.h b/boards/im880b/include/periph_conf.h index 28f3f41e7a..d4e2bfc464 100644 --- a/boards/im880b/include/periph_conf.h +++ b/boards/im880b/include/periph_conf.h @@ -23,7 +23,7 @@ * This board provides an LSE, so enable it before including the default clock config */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/lobaro-lorabox/include/periph_conf.h b/boards/lobaro-lorabox/include/periph_conf.h index 8451e16f3c..37aa291cc7 100644 --- a/boards/lobaro-lorabox/include/periph_conf.h +++ b/boards/lobaro-lorabox/include/periph_conf.h @@ -28,7 +28,7 @@ * This board provides an LSE, so enable it before including the default clock config */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/lsn50/include/periph_conf.h b/boards/lsn50/include/periph_conf.h index 1ff10d0d1a..8caf9b212c 100644 --- a/boards/lsn50/include/periph_conf.h +++ b/boards/lsn50/include/periph_conf.h @@ -21,7 +21,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/nucleo-l031k6/include/periph_conf.h b/boards/nucleo-l031k6/include/periph_conf.h index f4d270da8a..b1acd433c2 100644 --- a/boards/nucleo-l031k6/include/periph_conf.h +++ b/boards/nucleo-l031k6/include/periph_conf.h @@ -23,7 +23,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/nucleo-l053r8/include/periph_conf.h b/boards/nucleo-l053r8/include/periph_conf.h index 753d3362fc..4960222fb9 100644 --- a/boards/nucleo-l053r8/include/periph_conf.h +++ b/boards/nucleo-l053r8/include/periph_conf.h @@ -23,7 +23,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/boards/nucleo-l073rz/include/periph_conf.h b/boards/nucleo-l073rz/include/periph_conf.h index a24b128e2c..9a7a0918b4 100644 --- a/boards/nucleo-l073rz/include/periph_conf.h +++ b/boards/nucleo-l073rz/include/periph_conf.h @@ -23,7 +23,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" diff --git a/cpu/stm32/stmclk/stmclk_l0l1.c b/cpu/stm32/stmclk/stmclk_l0l1.c index 876631d128..c7d028f0bc 100644 --- a/cpu/stm32/stmclk/stmclk_l0l1.c +++ b/cpu/stm32/stmclk/stmclk_l0l1.c @@ -62,7 +62,7 @@ #endif /* Check the source to be used for the PLL */ -#if CONFIG_BOARD_HAS_HSE +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE) #else /* Use HSI as PLL input */ #define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI) @@ -155,16 +155,23 @@ void stmclk_init_sysclk(void) /* Wait Until the Voltage Regulator is ready */ while((PWR->CSR & PWR_CSR_VOSF) != 0) {} - if (CONFIG_USE_CLOCK_HSE) { - /* Enable the HSE clock now */ + /* Only enable the HSE clock when it's provided by the board and required: + - when HSE is used as system clock + - when PLL is used as system clock (because HSE is used automatically + as PLL input if it's available) + */ + if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && + (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_PLL))) { RCC->CR |= (RCC_CR_HSEON); while (!(RCC->CR & RCC_CR_HSERDY)) {} + } + if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) { /* Select HSE as system clock and configure the different prescalers */ RCC->CFGR &= ~(RCC_CFGR_SW); RCC->CFGR |= RCC_CFGR_SW_HSE; } - else if (CONFIG_USE_CLOCK_MSI) { + else if (IS_ACTIVE(CONFIG_USE_CLOCK_MSI)) { /* Configure MSI range and enable it */ RCC->ICSCR |= CLOCK_MSIRANGE; RCC->CR |= (RCC_CR_MSION); @@ -174,13 +181,7 @@ void stmclk_init_sysclk(void) RCC->CFGR &= ~(RCC_CFGR_SW); RCC->CFGR |= RCC_CFGR_SW_MSI; } - else if (CONFIG_USE_CLOCK_PLL) { - if (CONFIG_BOARD_HAS_HSE) { - /* if configured, we need to enable the HSE clock now */ - RCC->CR |= (RCC_CR_HSEON); - while (!(RCC->CR & RCC_CR_HSERDY)) {} - } - + else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) { /* Configure PLL clock source and configure the different prescalers */ RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); RCC->CFGR |= (CLOCK_PLL_SOURCE | CLOCK_PLL_DIV | CLOCK_PLL_MUL);