From 8bd90aaf00635b9251c179ef64ac983f8f68e9cc Mon Sep 17 00:00:00 2001
From: Antonio Galea <antonio.galea@gmail.com>
Date: Wed, 5 May 2021 10:56:37 +0200
Subject: [PATCH] cpu/saml21: fix timer skew for slow clocks

---
 cpu/saml21/cpu.c                | 10 +++++++---
 cpu/saml21/include/periph_cpu.h |  2 +-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/cpu/saml21/cpu.c b/cpu/saml21/cpu.c
index 449791e5ce..96a2b72703 100644
--- a/cpu/saml21/cpu.c
+++ b/cpu/saml21/cpu.c
@@ -99,8 +99,12 @@ uint32_t sam0_gclk_freq(uint8_t id)
     switch (id) {
     case SAM0_GCLK_MAIN:
         return CLOCK_CORECLOCK;
-    case SAM0_GCLK_8MHZ:
+    case SAM0_GCLK_TIMER:
+#if (CLOCK_CORECLOCK == 48000000U) || (CLOCK_CORECLOCK == 16000000U) || (CLOCK_CORECLOCK == 8000000U)
         return 8000000;
+#else
+        return 4000000;
+#endif
     case SAM0_GCLK_32KHZ:
         return 32768;
     case SAM0_GCLK_48MHZ:
@@ -292,8 +296,8 @@ void cpu_init(void)
         }
     }
     /* clock used by timers */
-    _gclk_setup(SAM0_GCLK_8MHZ, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
-                | GCLK_GENCTRL_DIV(2));
+    _gclk_setup(SAM0_GCLK_TIMER, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M
+                | GCLK_GENCTRL_DIV(CLOCK_CORECLOCK/sam0_gclk_freq(SAM0_GCLK_TIMER)));
 
 #ifdef MODULE_PERIPH_PM
     PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);
diff --git a/cpu/saml21/include/periph_cpu.h b/cpu/saml21/include/periph_cpu.h
index e383212ac3..9bf0dd50e6 100644
--- a/cpu/saml21/include/periph_cpu.h
+++ b/cpu/saml21/include/periph_cpu.h
@@ -44,7 +44,7 @@ extern "C" {
  */
 enum {
     SAM0_GCLK_MAIN  = 0,                 /**< Main clock */
-    SAM0_GCLK_8MHZ  = 1,                 /**< 8MHz clock */
+    SAM0_GCLK_TIMER = 1,                 /**< 4/8MHz clock for timers */
     SAM0_GCLK_32KHZ = 2,                 /**< 32 kHz clock */
     SAM0_GCLK_48MHZ = 3,                 /**< 48MHz clock */
 };