Adding Files for Stellaris Porting
This commit is contained in:
Rakendra Thapa
parent
0b673e66da
commit
8c1abd716d
18
boards/ek-lm4f120xl/dist/openocd.cfg
vendored
18
boards/ek-lm4f120xl/dist/openocd.cfg
vendored
@ -1 +1,17 @@
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source [find board/ek-lm4f120xl.cfg]
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#
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# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits
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#
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# http://www.ti.com/tool/ek-lm4f120xl
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#
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#
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# NOTE: using the bundled ICDI interface is optional!
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# This interface is not ftdi based as previous boards were
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#
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source [find interface/ti-icdi.cfg]
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transport select hla_jtag
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set WORKAREASIZE 0x8000
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set CHIPNAME lm4f120h5qr
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source [find target/stellaris.cfg]
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1896
cpu/lm4f120/1
1896
cpu/lm4f120/1
File diff suppressed because it is too large
Load Diff
@ -24,7 +24,10 @@
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#include "thread.h"
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#include "periph_conf.h"
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#include "periph/timer.h"
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#include "mutex.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/* guard file in case no timers are defined */
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#if TIMER_0_EN
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@ -41,20 +44,17 @@ int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int))
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{
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if (dev == TIMER_0) {
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config[dev].cb = callback; // User Function
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); //Activate Timer0
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_WTIMER0); // Activate Timer0
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WTIMER0_CTL_R &= ~0x00000001; // Disable timer0A during setup
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WTIMER0_CFG_R = TIMER_CFG_16_BIT;
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WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // | TIMER_TAMR_TACDIR); // Configure for periodic mode
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WTIMER0_TAPR_R = 39; // 1us timer0A
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WTIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD; // Configure for periodic mode
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WTIMER0_TAPR_R = TIMER_0_PRESCALER; // 1us timer0A
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WTIMER0_ICR_R = 0x00000001; // clear timer0A timeout flag
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WTIMER0_IMR_R |= 0x00000001; // arm timeout interrupt
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// NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
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ROM_IntPrioritySet(INT_WTIMER0A, 32);
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ROM_IntEnable(INT_WTIMER0A);
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ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT);
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// timer_irq_enable(dev);
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timer_irq_enable(dev);
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timer_start(dev);
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DEBUG("startTimeout Value=%lu\n", ROM_TimerValueGet(WTIMER0_BASE, TIMER_A));
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DEBUG("startTimeout Value=0x%lx\n", ROM_TimerValueGet(WTIMER0_BASE, TIMER_A));
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return 1;
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}
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return -1;
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@ -64,9 +64,9 @@ int timer_set(tim_t dev, int channel, unsigned int timeout)
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{
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if (dev == TIMER_0) {
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unsigned int now = timer_read(dev);
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DEBUG("timer_set now=%u\n",now);
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DEBUG("timer_set timeout=%u\n", timeout);
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return timer_set_absolute(dev, channel, HWTIMER_MAXTICKS-1-now+timeout);
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DEBUG("timer_set now=0x%x\n",now);
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DEBUG("timer_set timeout=0x%x\n", timeout);
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return timer_set_absolute(dev, channel, now+timeout);
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}
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return -1;
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}
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@ -75,7 +75,7 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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{
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if (dev == TIMER_0) {
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WTIMER0_TAILR_R = 0x00000000 | value; // period; Reload value
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DEBUG("Setting timer absolute value=%u\n", value);
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DEBUG("Setting timer absolute value=0x%x\n", value);
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return 1;
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}
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return -1;
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@ -84,7 +84,7 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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int timer_clear(tim_t dev, int channel)
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{
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if (dev == TIMER_0){
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WTIMER0_TAILR_R = 0x00000000; // period; Reload value
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WTIMER0_ICR_R = TIMER_ICR_TATOCINT; // clear timer0A timeout flag
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return 1;
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}
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return -1;
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@ -94,8 +94,11 @@ unsigned int timer_read(tim_t dev)
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{
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if (dev == TIMER_0) {
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unsigned int currTimer0Val=0;
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unsigned int loadTimer0Val=0;
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currTimer0Val = (unsigned int)ROM_TimerValueGet(WTIMER0_BASE, TIMER_A);
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return (HWTIMER_MAXTICKS - currTimer0Val);
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loadTimer0Val = (unsigned int)ROM_TimerLoadGet(WTIMER0_BASE, TIMER_A);
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DEBUG("WTIMER0_TAILR_R=0x%lx\t currTimer0Val=0x%x\t loadTimer0Val=0x%x\n", WTIMER0_TAILR_R, currTimer0Val, loadTimer0Val);
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return (loadTimer0Val - currTimer0Val);
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}
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return 0;
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}
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@ -103,7 +106,6 @@ unsigned int timer_read(tim_t dev)
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void timer_start(tim_t dev)
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{
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if (dev == TIMER_0) {
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DEBUG("Starting the timer\n");
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ROM_TimerEnable(WTIMER0_BASE, TIMER_A);
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}
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}
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@ -118,7 +120,6 @@ void timer_stop(tim_t dev)
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void timer_irq_enable(tim_t dev)
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{
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if (dev == TIMER_0) {
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DEBUG("Enabling Timer Interrupts\n");
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ROM_IntEnable(INT_WTIMER0A);
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ROM_TimerIntEnable(WTIMER0_BASE, TIMER_TIMA_TIMEOUT);
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}
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@ -127,7 +128,6 @@ void timer_irq_enable(tim_t dev)
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void timer_irq_disable(tim_t dev)
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{
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if (dev == TIMER_0) {
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DEBUG("Disabling Timer Interrupts\n");
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ROM_IntDisable(INT_WTIMER0A);
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}
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}
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@ -145,6 +145,7 @@ void TIMER0IntHandler(void)
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{
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TIMER0_ICR_R = TIMER_ICR_TATOCINT; // acknowledge timer0A timeout
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config[TIMER_0].cb(0);
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if (sched_context_switch_request){
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thread_yield();
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}
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@ -80,67 +80,15 @@ static const unsigned long g_ulUARTInt[3] =
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INT_UART2
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};
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int uart_init_testing(uart_t uart, uint32_t baudrate)
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{
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// Enable lazy stacking for interrupt handlers. This allows floating point instructions to be
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// used within interrupt handers, but at the expense of extra stack usuage.
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const unsigned long srcClock = ROM_SysCtlClockGet();
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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ROM_UARTDisable(UART0_BASE);
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ROM_UARTConfigSetExpClk(UART0_BASE,srcClock, baudrate,
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(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
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UART_CONFIG_WLEN_8));
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//Enable the UART interrupt
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ROM_UARTEnable(UART0_BASE);
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// Prompt for text to be entered.
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//
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//UARTSend((unsigned char *)"\033[2JEnter text: ", 16);
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//
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// Loop forever echoing data through the UART.
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//
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printf("Passed Testing\n");
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return 1;
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}
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void UARTSend(const unsigned char *pucBuffer, unsigned long ulCount)
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{
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//
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// Loop while there are more characters to send.
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//
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while(ulCount--)
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{
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//
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// Write the next character to the UART.
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//
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ROM_UARTCharPutNonBlocking(UART0_BASE, *pucBuffer++);
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}
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}
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/**********************************************************************************/
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/* Configuring the UART console
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*/
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
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{
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// The base address of the Choosen UART
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// unsigned long ulBase=0;
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// Check the arguments
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ASSERT(uart == 0);
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// Check to make sure the UART peripheral is present
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if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0))
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{
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if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)){
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return -1;
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}
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@ -149,13 +97,11 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t t
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return res;
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}
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/* save callbacks */
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config[uart].rx_cb = rx_cb;
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config[uart].tx_cb = tx_cb;
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config[uart].arg = arg;
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// Select the base address of the UART
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// ulBase = g_ulUARTBase[uart];
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// Configure the relevant UART pins for operations as a UART rather than GPIOs.
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@ -164,10 +110,15 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t t
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#if UART_0_EN
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case UART_0:
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NVIC_SetPriority(UART_0_IRQ_CHAN, UART_IRQ_PRIO);
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ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);
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ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8); // Set FIFO to 8 Characters
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ROM_UARTFIFOEnable(UART0_BASE); // Enable FIFOs
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// Enable the UART interrupt
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NVIC_EnableIRQ(UART_0_IRQ_CHAN);
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//ROM_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
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//ROM_IntEnable(INT_UART0);
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// Enable RX interrupt
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UART0_IM_R = UART_IM_RXIM | UART_IM_RTIM;
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break;
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#endif
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#if UART_1_EN
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@ -175,8 +126,6 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t t
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NVIC_SetPriority(UART_1_IRQ_CHAN, UART_IRQ_PRIO);
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// Enable the UART interrupt
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NVIC_EnableIRQ(UART_1_IRQ_CHAN);
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// ROM_UARTIntEnable(UART1_BASE, UART_INT_RX | UART_INT_RT);
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// ROM_IntEnable(INT_UART1);
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break;
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#endif
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}
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@ -199,6 +148,7 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
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(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
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UART_CONFIG_WLEN_8));
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ROM_UARTEnable(UART0_BASE);
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break;
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#endif
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@ -208,14 +158,14 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
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void uart_tx_begin(uart_t uart)
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{
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// enable TX interrupt
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ROM_UARTIntEnable(UART0_BASE, UART_INT_TX);
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uart_write(uart, '\0');
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UART0_IM_R |= UART_IM_TXIM;
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}
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int uart_write(uart_t uart, char data)
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{
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ROM_UARTCharPutNonBlocking(UART0_BASE, data);
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return 1;
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int ret=ROM_UARTCharPutNonBlocking(UART0_BASE, data);
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return ret;
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}
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int uart_read_blocking(uart_t uart, char *data)
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@ -254,16 +204,14 @@ void UARTIntHandler(void)
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// Get the interrupt status
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ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
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// Clear the asserted interrupts
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ROM_UARTIntClear(UART0_BASE, ulStatus);
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// Are we interrupted due to TX done
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if(ulStatus & UART_INT_TX)
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{
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// Turn off the Transmit Interrupt
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if (config[UART_0].tx_cb(config[UART_0].arg) == 0){
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ROM_UARTIntDisable(UART0_BASE, UART_INT_TX);
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UART0_IM_R &= ~UART_IM_TXIM;
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}
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}
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@ -283,8 +231,4 @@ void UARTIntHandler(void)
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thread_yield();
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}
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}
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#endif /* (UART_0_EN || UART_1_EN) */
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@ -1,315 +0,0 @@
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/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_lm4f120
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* @{
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*
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* @file startup.c - Startup code
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* @brief LM4F120H5QR startup code and interrupt vector definition.
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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/**
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* memory markers as defined in the linker script
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*/
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extern uint32_t _sfixed;
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extern uint32_t _efixed;
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extern uint32_t _etext;
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extern uint32_t _srelocate;
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extern uint32_t _erelocate;
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extern uint32_t _szero;
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extern uint32_t _ezero;
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extern uint32_t _sstack;
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extern uint32_t _estack;
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//-----------------------------------------------------------------------------
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// Functions declarations
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//-----------------------------------------------------------------------------
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void reset_handler(void);
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static void NmiSR(void);
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static void FaultISR(void);
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extern void empty_def_handler(void);
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extern void board_init(void);
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extern void kernel_init(void);
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extern void __libc_init_array(void);
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/**
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* Required by g++ cross compiler
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*/
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void *__dso_handle;
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// External declaration for the interrupt handler used by the application
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extern void UARTIntHandler(void); // UART 0 21
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extern void UART1IntHandler(void); // UART 1 21
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extern void TIMER0IntHandler(void); // 16 bit timer 0 A
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extern void WTIMER0IntHandler(void); // 32 bit timer 0 A
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extern void TIMER1IntHandler(void); // 16 bit timer 1 A
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extern void isr_svc(void); // SV call
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extern void isr_pendsv(void); // PendSV
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extern void isr_bus_fault(void); // Bus Fault
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extern void isr_usage_fault(void); // Usage Fault
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/* interrupt vector table */
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__attribute__ ((section(".vectors")))
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const void *interrupt_vector[] = {
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/* Stack pointer */
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(void*) (&_estack), /* pointer to the top of the empty stack */
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/* Cortex-M4 handlers */
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(void*) reset_handler, /* entry point of the program */
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NmiSR, // NMI handler. 2
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FaultISR, // hard fault handler. 3
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// Configurable priority interruts handler start here.
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empty_def_handler, // Memory Management Fault 4
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isr_bus_fault, // Bus Fault 5
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isr_usage_fault, // Usage Fault 6
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0, // Reserved 7
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0, // Reserved 8
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0, // Reserved 9
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0, // Reserved 10
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isr_svc, // SV call 11
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empty_def_handler, // Debug monitor 12
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0, // Reserved 13
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isr_pendsv, // PendSV 14
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empty_def_handler, // SysTick 15
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// Peripherial interrupts start here.
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empty_def_handler, // GPIO Port A 16
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empty_def_handler, // GPIO Port B 17
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empty_def_handler, // GPIO Port C 18
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empty_def_handler, // GPIO Port D 19
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empty_def_handler, // GPIO Port E 20
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UARTIntHandler, // UART 0 21
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UART1IntHandler, // UART 1 22
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empty_def_handler, // SSI 0 23
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empty_def_handler, // I2C 0 24
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0, // Reserved 25
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0, // Reserved 26
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0, // Reserved 27
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0, // Reserved 28
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0, // Reserved 29
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empty_def_handler, // ADC 0 Seq 0 30
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empty_def_handler, // ADC 0 Seq 1 31
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empty_def_handler, // ADC 0 Seq 2 32
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empty_def_handler, // ADC 0 Seq 3 33
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empty_def_handler, // WDT 0 and 1 34
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TIMER0IntHandler, // 16/32 bit timer 0 A 35
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empty_def_handler, // 16/32 bit timer 0 B 36
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TIMER1IntHandler, // 16/32 bit timer 1 A 37
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empty_def_handler, // 16/32 bit timer 1 B 38
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empty_def_handler, // 16/32 bit timer 2 A 39
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empty_def_handler, // 16/32 bit timer 2 B 40
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empty_def_handler, // Analog comparator 0 41
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empty_def_handler, // Analog comparator 1 42
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0, // Reserved 43
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empty_def_handler, // System control 44
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empty_def_handler, // Flash + EEPROM control 45
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empty_def_handler, // GPIO Port F 46
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0, // Reserved 47
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0, // Reserved 48
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empty_def_handler, // UART 2 49
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empty_def_handler, // SSI 1 50
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empty_def_handler, // 16/32 bit timer 3 A 51
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empty_def_handler, // 16/32 bit timer 3 B 52
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empty_def_handler, // I2C 1 53
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0, // Reserved 54
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empty_def_handler, // CAN 0 55
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0, // Reserved 56
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0, // Reserved 57
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0, // Reserved 58
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empty_def_handler, // Hibernation module 59
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empty_def_handler, // USB 60
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0, // Reserved 61
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empty_def_handler, // UDMA SW 62
|
||||
empty_def_handler, // UDMA Error 63
|
||||
empty_def_handler, // ADC 1 Seq 0 64
|
||||
empty_def_handler, // ADC 1 Seq 1 65
|
||||
empty_def_handler, // ADC 1 Seq 2 66
|
||||
empty_def_handler, // ADC 1 Seq 3 67
|
||||
0, // Reserved 68
|
||||
0, // Reserved 69
|
||||
0, // Reserved 70
|
||||
0, // Reserved 71
|
||||
0, // Reserved 72
|
||||
empty_def_handler, // SSI 2 73
|
||||
empty_def_handler, // SSI 2 74
|
||||
empty_def_handler, // UART 3 75
|
||||
empty_def_handler, // UART 4 76
|
||||
empty_def_handler, // UART 5 77
|
||||
empty_def_handler, // UART 6 78
|
||||
empty_def_handler, // UART 7 79
|
||||
0, // Reserved 80
|
||||
0, // Reserved 81
|
||||
0, // Reserved 82
|
||||
0, // Reserved 83
|
||||
empty_def_handler, // I2C 2 84
|
||||
empty_def_handler, // I2C 4 85
|
||||
empty_def_handler, // 16/32 bit timer 4 A 86
|
||||
empty_def_handler, // 16/32 bit timer 4 B 87
|
||||
0, // Reserved 88
|
||||
0, // Reserved 89
|
||||
0, // Reserved 90
|
||||
0, // Reserved 91
|
||||
0, // Reserved 92
|
||||
0, // Reserved 93
|
||||
0, // Reserved 94
|
||||
0, // Reserved 95
|
||||
0, // Reserved 96
|
||||
0, // Reserved 97
|
||||
0, // Reserved 98
|
||||
0, // Reserved 99
|
||||
0, // Reserved 100
|
||||
0, // Reserved 101
|
||||
0, // Reserved 102
|
||||
0, // Reserved 103
|
||||
0, // Reserved 104
|
||||
0, // Reserved 105
|
||||
0, // Reserved 106
|
||||
0, // Reserved 107
|
||||
empty_def_handler, // 16/32 bit timer 5 A 108
|
||||
empty_def_handler, // 16/32 bit timer 5 B 109
|
||||
WTIMER0IntHandler, // 32/64 bit timer 0 A 110
|
||||
empty_def_handler, // 32/64 bit timer 0 B 111
|
||||
empty_def_handler, // 32/64 bit timer 1 A 112
|
||||
empty_def_handler, // 32/64 bit timer 1 B 113
|
||||
empty_def_handler, // 32/64 bit timer 2 A 114
|
||||
empty_def_handler, // 32/64 bit timer 2 B 115
|
||||
empty_def_handler, // 32/64 bit timer 3 A 116
|
||||
empty_def_handler, // 32/64 bit timer 3 B 117
|
||||
empty_def_handler, // 32/64 bit timer 4 A 118
|
||||
empty_def_handler, // 32/64 bit timer 4 B 119
|
||||
empty_def_handler, // 32/64 bit timer 5 A 120
|
||||
empty_def_handler, // 32/64 bit timer 5 B 121
|
||||
empty_def_handler, // System Exception 122
|
||||
0, // Reserved 123
|
||||
0, // Reserved 124
|
||||
0, // Reserved 125
|
||||
0, // Reserved 126
|
||||
0, // Reserved 127
|
||||
0, // Reserved 128
|
||||
0, // Reserved 129
|
||||
0, // Reserved 130
|
||||
0, // Reserved 131
|
||||
0, // Reserved 132
|
||||
0, // Reserved 133
|
||||
0, // Reserved 134
|
||||
0, // Reserved 135
|
||||
0, // Reserved 136
|
||||
0, // Reserved 137
|
||||
0, // Reserved 138
|
||||
0, // Reserved 139
|
||||
0, // Reserved 140
|
||||
0, // Reserved 141
|
||||
0, // Reserved 142
|
||||
0, // Reserved 143
|
||||
0, // Reserved 144
|
||||
0, // Reserved 145
|
||||
0, // Reserved 146
|
||||
0, // Reserved 147
|
||||
0, // Reserved 148
|
||||
0, // Reserved 149
|
||||
0, // Reserved 150
|
||||
0, // Reserved 151
|
||||
0, // Reserved 152
|
||||
0, // Reserved 153
|
||||
0 // Reserved 154
|
||||
};
|
||||
//
|
||||
//-----------------------------------------------------------------------------
|
||||
// Function implementations.
|
||||
//-----------------------------------------------------------------------------
|
||||
/**
|
||||
* @brief This function is the entry point after a system reset
|
||||
*
|
||||
* After a system reset, the following steps are necessary and carried out:
|
||||
* 1. load data section from flash to ram
|
||||
* 2. overwrite uninitialized data section (BSS) with zeros
|
||||
* 3. initialize the newlib
|
||||
* 4. initialize the board (sync clock, setup std-IO)
|
||||
* 5. initialize and start RIOTs kernel
|
||||
*/
|
||||
|
||||
void reset_handler(void)
|
||||
{
|
||||
uint32_t *dst;
|
||||
uint32_t *src = &_etext;
|
||||
|
||||
/* load data section from flash to ram */
|
||||
for (dst = &_srelocate; dst < &_erelocate; ) {
|
||||
*(dst++) = *(src++);
|
||||
}
|
||||
|
||||
/* default bss section to zero */
|
||||
for (dst = &_szero; dst < &_ezero; ) {
|
||||
*(dst++) = 0;
|
||||
}
|
||||
|
||||
/* initialize the board and startup the kernel */
|
||||
board_init();
|
||||
/* initialize std-c library (this should be done after board_init) */
|
||||
__libc_init_array();
|
||||
/* startup the kernel */
|
||||
kernel_init();
|
||||
}
|
||||
|
||||
// NMI Exception handler code NVIC 2
|
||||
static
|
||||
void NmiSR(void){
|
||||
// Just loop forever, so if you want to debug the processor it's running.
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
// Hard fault handler code NVIC 3
|
||||
static
|
||||
void FaultISR(void){
|
||||
// Just loop forever, so if you want to debug the processor it's running.
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
void isr_bus_fault(void){ // Bus Fault
|
||||
// Bus fault handler code
|
||||
// Just loop forever, so if you want to debug the processor it's running.
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
void isr_usage_fault(void){ // Usage Fault
|
||||
// Usage fault handler code
|
||||
// Just loop forever, so if you want to debug the processor it's running.
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
// Empty handler used as default.
|
||||
void empty_def_handler(void){
|
||||
// Just loop forever, so if you want to debug the processor it's running.
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
void TIMER1IntHandler(void){
|
||||
// Just loop forever, so if you want to debug the processor it's running.
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
void UART1IntHandler(void){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
282
cpu/lm4f120/vectors.c
Normal file
282
cpu/lm4f120/vectors.c
Normal file
@ -0,0 +1,282 @@
|
||||
/*
|
||||
* Copyright (C) 2(void *) (0UL)14-2(void *) (0UL)15 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser General
|
||||
* Public License v2.1. See the file LICENSE in the top level directory for more
|
||||
* details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Interrupt vector definitions
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "vectors_cortexm.h"
|
||||
|
||||
/* get the start of the ISR stack as defined in the linkerscript */
|
||||
extern uint32_t _estack;
|
||||
|
||||
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||
* as the alias definition */
|
||||
void dummy_handler(void) {
|
||||
dummy_handler_default();
|
||||
}
|
||||
|
||||
/* Cortex-M common interrupt vectors */
|
||||
WEAK_DEFAULT void isr_svc(void);
|
||||
WEAK_DEFAULT void isr_pendsv(void);
|
||||
WEAK_DEFAULT void isr_systick(void);
|
||||
/* LM4F120 specific interrupt vectors */
|
||||
WEAK_DEFAULT void UARTIntHandler(void); // UART 0
|
||||
WEAK_DEFAULT void UART1IntHandler(void); // UART 1
|
||||
WEAK_DEFAULT void TIMER0IntHandler(void); // 16 bit timer 0 A
|
||||
WEAK_DEFAULT void WTIMER0IntHandler(void); // 32 bit timer 0 A
|
||||
WEAK_DEFAULT void TIMER1IntHandler(void); // 16 bit timer 1 A
|
||||
WEAK_DEFAULT void isr_wwdg(void);
|
||||
WEAK_DEFAULT void isr_pvd(void);
|
||||
WEAK_DEFAULT void isr_tamp_stamp(void);
|
||||
WEAK_DEFAULT void isr_rtc_wkup(void);
|
||||
WEAK_DEFAULT void isr_flash(void);
|
||||
WEAK_DEFAULT void isr_rcc(void);
|
||||
WEAK_DEFAULT void isr_exti(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream0(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream1(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream2(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream3(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream4(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream5(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream6(void);
|
||||
WEAK_DEFAULT void isr_adc(void);
|
||||
WEAK_DEFAULT void isr_can1_tx(void);
|
||||
WEAK_DEFAULT void isr_can1_rx0(void);
|
||||
WEAK_DEFAULT void isr_can1_rx1(void);
|
||||
WEAK_DEFAULT void isr_can1_sce(void);
|
||||
WEAK_DEFAULT void isr_tim1_brk_tim9(void);
|
||||
WEAK_DEFAULT void isr_tim1_up_tim10(void);
|
||||
WEAK_DEFAULT void isr_tim1_trg_com_tim11(void);
|
||||
WEAK_DEFAULT void isr_tim1_cc(void);
|
||||
WEAK_DEFAULT void isr_tim2(void);
|
||||
WEAK_DEFAULT void isr_tim3(void);
|
||||
WEAK_DEFAULT void isr_tim4(void);
|
||||
WEAK_DEFAULT void isr_i2c1_ev(void);
|
||||
WEAK_DEFAULT void isr_i2c1_er(void);
|
||||
WEAK_DEFAULT void isr_i2c2_ev(void);
|
||||
WEAK_DEFAULT void isr_i2c2_er(void);
|
||||
WEAK_DEFAULT void isr_spi1(void);
|
||||
WEAK_DEFAULT void isr_spi2(void);
|
||||
WEAK_DEFAULT void isr_usart1(void);
|
||||
WEAK_DEFAULT void isr_usart2(void);
|
||||
WEAK_DEFAULT void isr_usart3(void);
|
||||
WEAK_DEFAULT void isr_rtc_alarm(void);
|
||||
WEAK_DEFAULT void isr_otg_fs_wkup(void);
|
||||
WEAK_DEFAULT void isr_tim8_brk_tim12(void);
|
||||
WEAK_DEFAULT void isr_tim8_up_tim13(void);
|
||||
WEAK_DEFAULT void isr_tim8_trg_com_tim14(void);
|
||||
WEAK_DEFAULT void isr_tim8_cc(void);
|
||||
WEAK_DEFAULT void isr_dma1_stream7(void);
|
||||
WEAK_DEFAULT void isr_fsmc(void);
|
||||
WEAK_DEFAULT void isr_sdio(void);
|
||||
WEAK_DEFAULT void isr_tim5(void);
|
||||
WEAK_DEFAULT void isr_spi3(void);
|
||||
WEAK_DEFAULT void isr_uart4(void);
|
||||
WEAK_DEFAULT void isr_uart5(void);
|
||||
WEAK_DEFAULT void isr_tim6_dac(void);
|
||||
WEAK_DEFAULT void isr_tim7(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream0(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream1(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream2(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream3(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream4(void);
|
||||
WEAK_DEFAULT void isr_eth(void);
|
||||
WEAK_DEFAULT void isr_eth_wkup(void);
|
||||
WEAK_DEFAULT void isr_can2_tx(void);
|
||||
WEAK_DEFAULT void isr_can2_rx0(void);
|
||||
WEAK_DEFAULT void isr_can2_rx1(void);
|
||||
WEAK_DEFAULT void isr_can2_sce(void);
|
||||
WEAK_DEFAULT void isr_otg_fs(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream5(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream6(void);
|
||||
WEAK_DEFAULT void isr_dma2_stream7(void);
|
||||
WEAK_DEFAULT void isr_usart6(void);
|
||||
WEAK_DEFAULT void isr_i2c3_ev(void);
|
||||
WEAK_DEFAULT void isr_i2c3_er(void);
|
||||
WEAK_DEFAULT void isr_otg_hs_ep1_out(void);
|
||||
WEAK_DEFAULT void isr_otg_hs_ep1_in(void);
|
||||
WEAK_DEFAULT void isr_otg_hs_wkup(void);
|
||||
WEAK_DEFAULT void isr_otg_hs(void);
|
||||
WEAK_DEFAULT void isr_dcmi(void);
|
||||
WEAK_DEFAULT void isr_cryp(void);
|
||||
WEAK_DEFAULT void isr_hash_rng(void);
|
||||
WEAK_DEFAULT void isr_fpu(void);
|
||||
|
||||
/* interrupt vector table */
|
||||
ISR_VECTORS const void *interrupt_vector[] = {
|
||||
/* Exception stack pointer */
|
||||
(void*) (&_estack), /* pointer to the top of the stack */
|
||||
/* Cortex-M4 handlers */
|
||||
(void*) reset_handler_default, /* entry point of the program */
|
||||
(void*) nmi_default, /* non maskable interrupt handler */
|
||||
(void*) hard_fault_default, /* hard fault exception */
|
||||
(void*) mem_manage_default, /* memory manage exception */
|
||||
(void*) bus_fault_default, /* bus fault exception */
|
||||
(void*) usage_fault_default, /* usage fault exception */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) isr_svc, /* system call interrupt, in RIOT used for
|
||||
* switching into thread context on boot */
|
||||
(void*) debug_mon_default, /* debug monitor exception */
|
||||
(void*) (0UL), /* Reserved */
|
||||
(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
|
||||
* context switching is happening here */
|
||||
(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
|
||||
// Peripherial interrupts start here.
|
||||
(void *) dummy_handler, // GPIO Port A 16
|
||||
(void *) dummy_handler, // GPIO Port B 17
|
||||
(void *) dummy_handler, // GPIO Port C 18
|
||||
(void *) dummy_handler, // GPIO Port D 19
|
||||
(void *) dummy_handler, // GPIO Port E 20
|
||||
(void *) UARTIntHandler, // UART 0 21
|
||||
(void *) UART1IntHandler, // UART 1 22
|
||||
(void *) dummy_handler, // SSI 0 23
|
||||
(void *) dummy_handler, // I2C 0 24
|
||||
(void *) (0UL), // Reserved 25
|
||||
(void *) (0UL), // Reserved 26
|
||||
(void *) (0UL), // Reserved 27
|
||||
(void *) (0UL), // Reserved 28
|
||||
(void *) (0UL), // Reserved 29
|
||||
(void *) dummy_handler, // ADC 0 Seq 0 30
|
||||
(void *) dummy_handler, // ADC 0 Seq 1 31
|
||||
(void *) dummy_handler, // ADC 0 Seq 2 32
|
||||
(void *) dummy_handler, // ADC 0 Seq 3 33
|
||||
(void *) dummy_handler, // WDT 0 and 1 34
|
||||
(void *) TIMER0IntHandler, // 16/32 bit timer 0 A 35
|
||||
(void *) dummy_handler, // 16/32 bit timer 0 B 36
|
||||
(void *) TIMER1IntHandler, // 16/32 bit timer 1 A 37
|
||||
(void *) dummy_handler, // 16/32 bit timer 1 B 38
|
||||
(void *) dummy_handler, // 16/32 bit timer 2 A 39
|
||||
(void *) dummy_handler, // 16/32 bit timer 2 B 40
|
||||
(void *) dummy_handler, // Analog comparator 0 41
|
||||
(void *) dummy_handler, // Analog comparator 1 42
|
||||
(void *) (0UL), // Reserved 43
|
||||
(void *) dummy_handler, // System control 44
|
||||
(void *) dummy_handler, // Flash + EEPROM control 45
|
||||
(void *) dummy_handler, // GPIO Port F 46
|
||||
(void *) (0UL), // Reserved 47
|
||||
(void *) (0UL), // Reserved 48
|
||||
(void *) dummy_handler, // UART 2 49
|
||||
(void *) dummy_handler, // SSI 1 50
|
||||
(void *) dummy_handler, // 16/32 bit timer 3 A 51
|
||||
(void *) dummy_handler, // 16/32 bit timer 3 B 52
|
||||
(void *) dummy_handler, // I2C 1 53
|
||||
(void *) (0UL), // Reserved 54
|
||||
(void *) dummy_handler, // CAN 0 55
|
||||
(void *) (0UL), // Reserved 56
|
||||
(void *) (0UL), // Reserved 57
|
||||
(void *) (0UL), // Reserved 58
|
||||
(void *) dummy_handler, // Hibernation module 59
|
||||
(void *) dummy_handler, // USB 60
|
||||
(void *) (0UL), // Reserved 61
|
||||
(void *) dummy_handler, // UDMA SW 62
|
||||
(void *) dummy_handler, // UDMA Error 63
|
||||
(void *) dummy_handler, // ADC 1 Seq 0) 64
|
||||
(void *) dummy_handler, // ADC 1 Seq 1 65
|
||||
(void *) dummy_handler, // ADC 1 Seq 2 66
|
||||
(void *) dummy_handler, // ADC 1 Seq 3 67
|
||||
(void *) (0UL), // Reserved 68
|
||||
(void *) (0UL), // Reserved 69
|
||||
(void *) (0UL), // Reserved 70
|
||||
(void *) (0UL), // Reserved 71
|
||||
(void *) (0UL), // Reserved 72
|
||||
(void *) dummy_handler, // SSI 2 73
|
||||
(void *) dummy_handler, // SSI 2 74
|
||||
(void *) dummy_handler, // UART 3 75
|
||||
(void *) dummy_handler, // UART 4 76
|
||||
(void *) dummy_handler, // UART 5 77
|
||||
(void *) dummy_handler, // UART 6 78
|
||||
(void *) dummy_handler, // UART 7 79
|
||||
(void *) (0UL), // Reserved 80
|
||||
(void *) (0UL), // Reserved 81
|
||||
(void *) (0UL), // Reserved 82
|
||||
(void *) (0UL), // Reserved 83
|
||||
(void *) dummy_handler, // I2C 2 84
|
||||
(void *) dummy_handler, // I2C 4 85
|
||||
(void *) dummy_handler, // 16/32 bit timer 4 A 86
|
||||
(void *) dummy_handler, // 16/32 bit timer 4 B 87
|
||||
(void *) (0UL), // Reserved 88
|
||||
(void *) (0UL), // Reserved 89
|
||||
(void *) (0UL), // Reserved 90
|
||||
(void *) (0UL), // Reserved 91
|
||||
(void *) (0UL), // Reserved 92
|
||||
(void *) (0UL), // Reserved 93
|
||||
(void *) (0UL), // Reserved 94
|
||||
(void *) (0UL), // Reserved 95
|
||||
(void *) (0UL), // Reserved 96
|
||||
(void *) (0UL), // Reserved 97
|
||||
(void *) (0UL), // Reserved 98
|
||||
(void *) (0UL), // Reserved 99
|
||||
(void *) (0UL), // Reserved 100
|
||||
(void *) (0UL), // Reserved 101
|
||||
(void *) (0UL), // Reserved 102
|
||||
(void *) (0UL), // Reserved 103
|
||||
(void *) (0UL), // Reserved 104
|
||||
(void *) (0UL), // Reserved 105
|
||||
(void *) (0UL), // Reserved 106
|
||||
(void *) (0UL), // Reserved 107
|
||||
(void *) dummy_handler, // 16/32 bit timer 5 A 108
|
||||
(void *) dummy_handler, // 16/32 bit timer 5 B 109
|
||||
(void *) WTIMER0IntHandler, // 32/64 bit timer 0 A 110
|
||||
(void *) dummy_handler, // 32/64 bit timer 0 B 111
|
||||
(void *) dummy_handler, // 32/64 bit timer 1 A 112
|
||||
(void *) dummy_handler, // 32/64 bit timer 1 B 113
|
||||
(void *) dummy_handler, // 32/64 bit timer 2 A 114
|
||||
(void *) dummy_handler, // 32/64 bit timer 2 B 115
|
||||
(void *) dummy_handler, // 32/64 bit timer 3 A 116
|
||||
(void *) dummy_handler, // 32/64 bit timer 3 B 117
|
||||
(void *) dummy_handler, // 32/64 bit timer 4 A 118
|
||||
(void *) dummy_handler, // 32/64 bit timer 4 B 119
|
||||
(void *) dummy_handler, // 32/64 bit timer 5 A 120
|
||||
(void *) dummy_handler, // 32/64 bit timer 5 B 121
|
||||
(void *) dummy_handler, // System Exception 122
|
||||
(void *) (0UL), // Reserved 123
|
||||
(void *) (0UL), // Reserved 124
|
||||
(void *) (0UL), // Reserved 125
|
||||
(void *) (0UL), // Reserved 126
|
||||
(void *) (0UL), // Reserved 127
|
||||
(void *) (0UL), // Reserved 128
|
||||
(void *) (0UL), // Reserved 129
|
||||
(void *) (0UL), // Reserved 130
|
||||
(void *) (0UL), // Reserved 131
|
||||
(void *) (0UL), // Reserved 132
|
||||
(void *) (0UL), // Reserved 133
|
||||
(void *) (0UL), // Reserved 134
|
||||
(void *) (0UL), // Reserved 135
|
||||
(void *) (0UL), // Reserved 136
|
||||
(void *) (0UL), // Reserved 137
|
||||
(void *) (0UL), // Reserved 138
|
||||
(void *) (0UL), // Reserved 139
|
||||
(void *) (0UL), // Reserved 140
|
||||
(void *) (0UL), // Reserved 141
|
||||
(void *) (0UL), // Reserved 142
|
||||
(void *) (0UL), // Reserved 143
|
||||
(void *) (0UL), // Reserved 144
|
||||
(void *) (0UL), // Reserved 145
|
||||
(void *) (0UL), // Reserved 146
|
||||
(void *) (0UL), // Reserved 147
|
||||
(void *) (0UL), // Reserved 148
|
||||
(void *) (0UL), // Reserved 149
|
||||
(void *) (0UL), // Reserved 150
|
||||
(void *) (0UL), // Reserved 151
|
||||
(void *) (0UL), // Reserved 152
|
||||
(void *) (0UL), // Reserved 153
|
||||
(void *) (0UL) // Reserved 154
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user