From 190f3190668e0663acf548cd906d21dd6c6aaae5 Mon Sep 17 00:00:00 2001
From: Hauke Petersen <hauke.petersen@fu-berlin.de>
Date: Tue, 28 Mar 2017 20:00:03 +0200
Subject: [PATCH] cpu/sam0|stm32: use common cortexm_sleep()

---
 cpu/samd21/periph/pm.c       | 12 ++++--------
 cpu/saml21/periph/pm.c       |  5 +----
 cpu/stm32_common/periph/pm.c | 15 +++++----------
 3 files changed, 10 insertions(+), 22 deletions(-)

diff --git a/cpu/samd21/periph/pm.c b/cpu/samd21/periph/pm.c
index 8af3775d70..3ab020f3c0 100644
--- a/cpu/samd21/periph/pm.c
+++ b/cpu/samd21/periph/pm.c
@@ -52,38 +52,34 @@ enum system_sleepmode {
 
 void pm_set(unsigned mode)
 {
+    int deep = 0;
+
     switch (mode) {
         case 0:
             /* Standby Mode
              * Potential Wake Up sources: asynchronous
              */
-            SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+            deep = 1;
             break;
         case 1:
             /* Sleep mode Idle 2
              * Potential Wake Up sources: asynchronous
              */
-            SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
             PM->SLEEP.reg = SYSTEM_SLEEPMODE_IDLE_2;
             break;
         case 2:
             /* Sleep mode Idle 1
              * Potential Wake Up sources: Synchronous (APB), asynchronous
              */
-            SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
             PM->SLEEP.reg = SYSTEM_SLEEPMODE_IDLE_1;
             break;
         case 3:
             /* Sleep mode Idle 0
              * Potential Wake Up sources: Synchronous (APB, AHB), asynchronous
             */
-            SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
             PM->SLEEP.reg = SYSTEM_SLEEPMODE_IDLE_0;
             break;
     }
 
-    /* Executes a device DSB (Data Synchronization Barrier) */
-    __DSB();
-    /* Enter standby mode */
-    __WFI();
+    cortexm_sleep(deep);
 }
diff --git a/cpu/saml21/periph/pm.c b/cpu/saml21/periph/pm.c
index 341459f953..2ff921f735 100644
--- a/cpu/saml21/periph/pm.c
+++ b/cpu/saml21/periph/pm.c
@@ -49,8 +49,5 @@ void pm_set(unsigned mode)
         while (PM->SLEEPCFG.bit.SLEEPMODE != _mode) {}
     }
 
-    /* Executes a device DSB (Data Synchronization Barrier) */
-    __DSB();
-    /* Enter standby mode */
-    __WFI();
+    cortexm_sleep(0);
 }
diff --git a/cpu/stm32_common/periph/pm.c b/cpu/stm32_common/periph/pm.c
index 93a5ff47fc..1c72bbfc09 100644
--- a/cpu/stm32_common/periph/pm.c
+++ b/cpu/stm32_common/periph/pm.c
@@ -30,6 +30,8 @@
 
 void pm_set(unsigned mode)
 {
+    int deep = 0;
+
 /* I just copied it from stm32f1/2/4, but I suppose it would work for the
  * others... /KS */
 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
@@ -40,26 +42,19 @@ void pm_set(unsigned mode)
             /* Enable WKUP pin to use for wakeup from standby mode */
             PWR->CSR |= PWR_CSR_EWUP;
             /* Set SLEEPDEEP bit of system control block */
-            SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+            deep = 1;
             break;
         case 1:                 /* STM Stop mode */
             /* Clear PDDS and LPDS bits to enter stop mode on */
             /* deepsleep with voltage regulator on */
             PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS);
             /* Set SLEEPDEEP bit of system control block */
-            SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-            break;
-        case 2:                  /* STM Sleep mode */
-            /* Reset SLEEPDEEP bit of system control block */
-            SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
+            deep = 1;
             break;
     }
 #endif
 
-    /* Executes a device DSB (Data Synchronization Barrier) */
-    __DSB();
-    /* Enter standby mode */
-    __WFI();
+    cortexm_sleep(deep);
 }
 
 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)