From 8f39a4a31045e59c2b4541d2fcf72d2f31c00f5a Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Thu, 27 Aug 2020 16:01:10 +0200 Subject: [PATCH] boards/stm32l1: use shared clock configuration header --- boards/im880b/Makefile.include | 3 ++ boards/im880b/include/periph_conf.h | 37 ++++---------------- boards/limifrog-v1/Makefile.include | 3 ++ boards/limifrog-v1/include/periph_conf.h | 25 +------------- boards/lobaro-lorabox/include/periph_conf.h | 38 +++++---------------- boards/nucleo-l152re/include/periph_conf.h | 35 +------------------ boards/nz32-sc151/include/periph_conf.h | 25 +------------- 7 files changed, 24 insertions(+), 142 deletions(-) diff --git a/boards/im880b/Makefile.include b/boards/im880b/Makefile.include index acda956bed..af98ff23c0 100644 --- a/boards/im880b/Makefile.include +++ b/boards/im880b/Makefile.include @@ -1,3 +1,6 @@ +# this board uses shared STM32 configuration snippets +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyUSB0 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) diff --git a/boards/im880b/include/periph_conf.h b/boards/im880b/include/periph_conf.h index cab463da5f..2c330bf3f4 100644 --- a/boards/im880b/include/periph_conf.h +++ b/boards/im880b/include/periph_conf.h @@ -19,42 +19,19 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H -#include "periph_cpu.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name Clock system configuration - * @{ - **/ -#define CLOCK_HSE (16000000U) /* external oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ - /* - * 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) + * This board provides an LSE, so enable it before including the default clock config */ #ifndef CLOCK_LSE #define CLOCK_LSE (1) #endif -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSE / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -/** @} */ +#include "periph_cpu.h" +#include "l1/cfg_clock_default.h" + +#ifdef __cplusplus +extern "C" { +#endif /** * @name Timer configuration diff --git a/boards/limifrog-v1/Makefile.include b/boards/limifrog-v1/Makefile.include index 8458a10af3..cbb09c40f1 100644 --- a/boards/limifrog-v1/Makefile.include +++ b/boards/limifrog-v1/Makefile.include @@ -1,3 +1,6 @@ +# this board uses shared STM32 configuration snippets +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyUSB0 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) diff --git a/boards/limifrog-v1/include/periph_conf.h b/boards/limifrog-v1/include/periph_conf.h index 076f88d397..62d92ff8ca 100644 --- a/boards/limifrog-v1/include/periph_conf.h +++ b/boards/limifrog-v1/include/periph_conf.h @@ -20,35 +20,12 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l1/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock system configuration - * @{ - **/ -#define CLOCK_HSI (16000000U) /* internal oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ - -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY - -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -/** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/lobaro-lorabox/include/periph_conf.h b/boards/lobaro-lorabox/include/periph_conf.h index 1e6f3ec3ba..64c8a47003 100644 --- a/boards/lobaro-lorabox/include/periph_conf.h +++ b/boards/lobaro-lorabox/include/periph_conf.h @@ -24,43 +24,21 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* + * This board provides an LSE, so enable it before including the default clock config + */ +#ifndef CLOCK_LSE +#define CLOCK_LSE (1) +#endif + #include "periph_cpu.h" +#include "l1/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock system configuration - * @{ - **/ -#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */ -/* - * 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) - */ -#ifndef CLOCK_LSE -#define CLOCK_LSE (1) -#endif -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY - -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-l152re/include/periph_conf.h b/boards/nucleo-l152re/include/periph_conf.h index 713540505c..1ef9319431 100644 --- a/boards/nucleo-l152re/include/periph_conf.h +++ b/boards/nucleo-l152re/include/periph_conf.h @@ -21,46 +21,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l1/cfg_clock_default.h" #include "cfg_timer_tim5.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock system configuration - * @{ - **/ -#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */ -/* - * 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) - * - * LSE might not be available by default in early (C-01) Nucleo boards. - * For newer revisions, an LSE crystal is present and CLOCK_LSE can be set to 1 - * if one wants to use it. - */ -#ifndef CLOCK_LSE -#define CLOCK_LSE (0) -#endif -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY - -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -/** @} */ - /** * @name DMA streams configuration * @{ diff --git a/boards/nz32-sc151/include/periph_conf.h b/boards/nz32-sc151/include/periph_conf.h index 821fb7357f..d26307a3a6 100644 --- a/boards/nz32-sc151/include/periph_conf.h +++ b/boards/nz32-sc151/include/periph_conf.h @@ -20,36 +20,13 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "l1/cfg_clock_default.h" #include "cfg_timer_tim5.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock system configuration - * @{ - **/ -#define CLOCK_HSI (16000000U) /* internal oscillator */ -#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ - -/* configuration of PLL prescaler and multiply values */ -/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ -#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 -#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 -/* configuration of peripheral bus clock prescalers */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ -/* configuration of flash access cycles */ -#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY - -/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) -/** @} */ - /** * @name UART configuration * @{