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* added proper "struct TMR_struct*" in hwtimer_cpu.c

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* removed dublicate definition of the UART structure in mc1322x.h
This commit is contained in:
Thomas Eichinger 2013-07-23 10:36:16 +02:00
parent ee6d1e1604
commit 92adb3e401
2 changed files with 12 additions and 91 deletions
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18
cpu/mc1322x/hwtimer_cpu.c
View File

@ -17,7 +17,7 @@
/* High level interrupt handler */
static void (*int_handler)(int);
void timer_x_init(TMR_struct* TMRx) {
void timer_x_init(volatile struct TMR_struct* const TMRx) {
/* Reset the timer */
TMRx->ENBL = 0;
/* Clear status */
@ -47,7 +47,7 @@ void timer_x_init(TMR_struct* TMRx) {
TMRx->ENBL = 0xf; /* enable all the timers --- why not? */
/* TODO: install ISR */
};
}
void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) {
int_handler = handler;
@ -59,26 +59,28 @@ void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) {
timer_x_init(TMR1);
timer_x_init(TMR2);
timer_x_init(TMR3);
};
}
/*---------------------------------------------------------------------------*/
void hwtimer_arch_enable_interrupt(void) {
/* this enables timer interrupts in general by using the ITC.
* Timer specific interrupt control is given by the TMRx structs. */
enable_irq(TRM);
//enable_irq(INT_NUM_TMR);
ITC->INTENABLEbits.TMR = 1;
}
/*---------------------------------------------------------------------------*/
void hwtimer_arch_disable_interrupt(void) {
/* this disables timer interrupts in general by using the ITC.
* Timer specific interrupt control is given by the TMRx structs. */
disable_irq(TRM);
//disable_irq(INT_NUM_TMR);
ITC->INTENABLEbits.TMR = 1;
}
/*---------------------------------------------------------------------------*/
void hwtimer_arch_set(unsigned long offset, short timer) {
/* get corresponding struct for the given ::timer parameter */
TMR_struct* tmr = (void *) TMR_BASE + (timer + TMR_OFFSET);
struct TMR_struct* tmr = (void *) TMR_BASE + (timer + TMR_OFFSET);
/* disable IRQs and save the status register */
unsigned long cpsr = disableIRQ();
@ -95,7 +97,7 @@ void hwtimer_arch_set(unsigned long offset, short timer) {
/*---------------------------------------------------------------------------*/
void hwtimer_arch_set_absolute(unsigned long value, short timer) {
/* get corresponding struct for the given ::timer parameter */
TMR_struct* tmr = (void *) TMR_BASE + (timer + TMR_OFFSET);
struct TMR_struct* tmr = (void *) TMR_BASE + (timer + TMR_OFFSET);
/* disable IRQs and save the status register */
unsigned long cpsr = disableIRQ();
@ -112,7 +114,7 @@ void hwtimer_arch_set_absolute(unsigned long value, short timer) {
/*---------------------------------------------------------------------------*/
void hwtimer_arch_unset(short timer) {
/* get corresponding struct for the given ::timer parameter */
TMR_struct* tmr = (void *) TMR_BASE + (timer + TMR_OFFSET);
struct TMR_struct* tmr = (void *) TMR_BASE + (timer + TMR_OFFSET);
tmr->CSCTRLbits.TCF1 = 0; /* reset compare flag */
tmr->CSCTRLbits.TCF1EN = 0; /* disable interrupts for TCF1 */

85
cpu/mc1322x/include/mc1322x.h
View File

@ -302,87 +302,6 @@ static volatile struct TMR_struct * const TMR3 = (void *) (TMR3_BASE);
/* Get timer number from the timer pointer. */
#define TMR_NUM(x) (((uint32_t)(x) - TMR_BASE) / TMR_OFFSET)
/*-----------------------------------------------------------------*/
/* UART */
#define UART1_BASE (0x80005000)
#define UART2_BASE (0x8000B000)
struct UART_struct {
union {
uint32_t CON;
struct UART_CON {
uint32_t :16;
uint32_t TST:1;
uint32_t MRXR:1;
uint32_t MTXR:1;
uint32_t FCE:1;
uint32_t FCP:1;
uint32_t XTIM:1;
uint32_t :2;
uint32_t TXOENB:1;
uint32_t CONTX:1;
uint32_t SB:1;
uint32_t ST2:1;
uint32_t EP:1;
uint32_t PEN:1;
uint32_t RXE:1;
uint32_t TXE:1;
} CONbits;
};
union {
uint32_t STAT;
struct UART_STAT {
uint32_t :24;
uint32_t TXRDY:1;
uint32_t RXRDY:1;
uint32_t RUE:1;
uint32_t ROE:1;
uint32_t TOE:1;
uint32_t FE:1;
uint32_t PE:1;
uint32_t SE:1;
} USTATbits;
};
union {
uint32_t DATA;
struct UART_DATA {
uint32_t :24;
uint32_t DATA:8;
} DATAbits;
};
union {
uint32_t RXCON;
struct UART_URXCON {
uint32_t :26;
uint32_t LVL:6;
} RXCONbits;
};
union {
uint32_t TXCON;
struct UART_TXCON {
uint32_t :26;
uint32_t LVL:6;
} TXCONbits;
};
union {
uint32_t CTS;
struct UART_CTS {
uint32_t :27;
uint32_t LVL:5;
} CTSbits;
};
union {
uint32_t BR;
struct UART_BR {
uint32_t INC:16;
uint32_t MOD:16;
} BRbits;
};
};
static volatile struct UART_struct * const UART1 = (void *) (UART1_BASE);
static volatile struct UART_struct * const UART2 = (void *) (UART2_BASE);
/*-----------------------------------------------------------------*/
/* Interrupts */
#define INTBASE (0x80020000)
@ -472,8 +391,8 @@ enum interrupt_nums {
#define global_irq_disable() (set_bit(*INTCNTL,20))
#define global_irq_enable() (clear_bit(*INTCNTL,20))
#define enable_irq(irq) (*INTENNUM = INT_NUM_##irq)
#define disable_irq(irq) (*INTDISNUM = INT_NUM_##irq)
#define enable_irq(irq) (*INTENNUM = irq)
#define disable_irq(irq) (*INTDISNUM = irq)
#define safe_irq_disable(x) volatile uint32_t saved_irq; saved_irq = *INTENABLE; disable_irq(x)
#define irq_restore() *INTENABLE = saved_irq