board: Initial import of stm32f3discovery
This commit is contained in:
Hauke Petersen
parent
c5c860f435
commit
94848cf57f
4
boards/stm32f3discovery/Makefile
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4
boards/stm32f3discovery/Makefile
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@ -0,0 +1,4 @@
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# tell the Makefile.base which module to build
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MODULE = $(BOARD)_base
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include $(RIOTBASE)/Makefile.base
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47
boards/stm32f3discovery/Makefile.include
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47
boards/stm32f3discovery/Makefile.include
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@ -0,0 +1,47 @@
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# define the cpu used by the stm32f3-discovery board
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export CPU = stm32f3
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export CPU_MODEL = stm32f303vc
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#define the default port depending on the host OS
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OS := $(shell uname)
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ifeq ($(OS),Linux)
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PORT ?= /dev/ttyUSB0
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else ifeq ($(OS),Darwin)
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PORT ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
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else
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$(info CAUTION: No flash tool for your host system found!)
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# TODO: add support for windows as host platform
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endif
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export PORT
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# define tools used for building the project
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export PREFIX = arm-none-eabi-
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export CC = $(PREFIX)gcc
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export AR = $(PREFIX)ar
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export AS = $(PREFIX)as
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export LINK = $(PREFIX)gcc
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export SIZE = $(PREFIX)size
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export OBJCOPY = $(PREFIX)objcopy
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export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm.py
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export FLASHER = st-flash
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export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh
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# define build specific options
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CPU_USAGE = -mcpu=cortex-m4
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FPU_USAGE = -mfloat-abi=hard -mfpu=fpv4-sp-d16
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export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles
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export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin
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export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian
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export LINKFLAGS += -g3 -ggdb -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles
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export LINKFLAGS += -T$(LINKERSCRIPT)
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export OFLAGS = -O binary
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export FFLAGS = write bin/$(BOARD)/$(APPLICATION).hex 0x8000000
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export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(BINDIR)/$(APPLICATION).elf
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# use newLib nano-specs if available
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ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null </dev/null ; echo $$?),0)
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export LINKFLAGS += -specs=nano.specs -lc -lnosys
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endif
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# export board specific includes to the global includes-listing
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export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include
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67
boards/stm32f3discovery/board.c
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67
boards/stm32f3discovery/board.c
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@ -0,0 +1,67 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_stm32f3discovery
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* @{
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*
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* @file
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* @brief Board specific implementations for the STM32F3Discovery evaluation board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "board.h"
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static void leds_init(void);
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void board_init(void)
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{
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/* initialize the boards LEDs */
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leds_init();
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/* initialize the CPU */
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cpu_init();
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}
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/**
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* @brief Initialize the boards on-board LEDs (LD3 to LD10)
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*
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* The LED initialization is hard-coded in this function. As the LEDs are soldered
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* onto the board they are fixed to their CPU pins.
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*
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* The LEDs are connected to the following pins:
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* - LD3: PE9
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* - LD4: PE8
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* - LD5: PE10
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* - LD6: PE15
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* - LD7: PE11
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* - LD8: PE14
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* - LD9: PE12
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* - LD10: PE13
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*/
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static void leds_init(void)
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{
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/* enable clock for port GPIOE */
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RCC->AHBENR |= RCC_AHBENR_GPIOEEN;
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/* set output speed to 50MHz */
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LED_PORT->OSPEEDR |= 0xffff0000;
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/* set output type to push-pull */
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LED_PORT->OTYPER &= ~(0x0000ff00);
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/* configure pins as general outputs */
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LED_PORT->MODER &= ~(0xffff0000);
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LED_PORT->MODER |= 0x55550000;
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/* disable pull resistors */
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LED_PORT->PUPDR &= ~(0xffff0000);
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/* turn all LEDs off */
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LED_PORT->BRR = 0xff00;
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}
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4
boards/stm32f3discovery/dist/debug.sh
vendored
Executable file
4
boards/stm32f3discovery/dist/debug.sh
vendored
Executable file
@ -0,0 +1,4 @@
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#!/bin/sh
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echo "Debugging $1"
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arm-none-eabi-gdb -tui -command=$1 $2
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1
boards/stm32f3discovery/dist/gdb.conf
vendored
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1
boards/stm32f3discovery/dist/gdb.conf
vendored
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@ -0,0 +1 @@
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tar extended-remote :4242
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103
boards/stm32f3discovery/include/board.h
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103
boards/stm32f3discovery/include/board.h
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@ -0,0 +1,103 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup board_stm32f3discovery STM32F3Discovery
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* @ingroup boards
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* @brief Board specific files for the STM32F3Discovery board
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* @{
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*
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* @file
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* @brief Board specific definitions for the STM32F3Discovery evaluation board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef __BOARD_H
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#define __BOARD_H
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#include "cpu.h"
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/**
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* Define the nominal CPU core clock in this board
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*/
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#define F_CPU (72000000UL)
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/**
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* @name Assign the hardware timer
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*/
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#define HW_TIMER TIMER_0
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/**
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* @name Define the UART used for stdio
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* @{
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*/
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#define STDIO UART_0
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#define STDIO_BAUDRATE (115200U)
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#define STDIO_BUFSIZE (64U)
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/** @} */
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/**
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* @name LED pin definitions
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* @{
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*/
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#define LED_PORT GPIOE
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#define LD3_PIN (1 << 9)
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#define LD4_PIN (1 << 8)
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#define LD5_PIN (1 << 10)
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#define LD6_PIN (1 << 15)
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#define LD7_PIN (1 << 11)
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#define LD8_PIN (1 << 14)
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#define LD9_PIN (1 << 12)
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#define LD10_PIN (1 << 13)
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/** @} */
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/**
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* @name Macros for controlling the on-board LEDs.
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* @{
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*/
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#define LD3_ON (LED_PORT->BSRRL = LD3_PIN)
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#define LD3_OFF (LED_PORT->BSRRH = LD3_PIN)
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#define LD3_TOGGLE (LED_PORT->ODR ^= LD3_PIN)
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#define LD4_ON (LED_PORT->BSRRL = LD4_PIN)
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#define LD4_OFF (LED_PORT->BSRRH = LD4_PIN)
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#define LD4_TOGGLE (LED_PORT->ODR ^= LD4_PIN)
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#define LD5_ON (LED_PORT->BSRRL = LD5_PIN)
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#define LD5_OFF (LED_PORT->BSRRH = LD5_PIN)
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#define LD5_TOGGLE (LED_PORT->ODR ^= LD5_PIN)
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#define LD6_ON (LED_PORT->BSRRL = LD6_PIN)
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#define LD6_OFF (LED_PORT->BSRRH = LD6_PIN)
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#define LD6_TOGGLE (LED_PORT->ODR ^= LD6_PIN)
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#define LD7_ON (LED_PORT->BSRRL = LD7_PIN)
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#define LD7_OFF (LED_PORT->BSRRH = LD7_PIN)
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#define LD7_TOGGLE (LED_PORT->ODR ^= LD7_PIN)
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#define LD8_ON (LED_PORT->BSRRL = LD8_PIN)
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#define LD8_OFF (LED_PORT->BSRRH = LD8_PIN)
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#define LD8_TOGGLE (LED_PORT->ODR ^= LD8_PIN)
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#define LD9_ON (LED_PORT->BSRRL = LD9_PIN)
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#define LD9_OFF (LED_PORT->BSRRH = LD9_PIN)
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#define LD9_TOGGLE (LED_PORT->ODR ^= LD9_PIN)
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#define LD10_ON (LED_PORT->BSRRL = LD10_PIN)
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#define LD10_OFF (LED_PORT->BSRRH = LD10_PIN)
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#define LD10_TOGGLE (LED_PORT->ODR ^= LD10_PIN)
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/* for compatability to other boards */
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#define LED_GREEN_ON LD4_ON
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#define LED_GREEN_OFF LD4_OFF
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#define LED_GREEN_TOGGLE LD4_TOGGLE
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#define LED_RED_ON LD5_ON
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#define LED_RED_OFF LD5_OFF
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#define LED_RED_TOGGLE LD5_TOGGLE
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#endif /** __BOARD_H */
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/** @} */
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232
boards/stm32f3discovery/include/periph_conf.h
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232
boards/stm32f3discovery/include/periph_conf.h
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@ -0,0 +1,232 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_stm32f3discovery
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the STM32F3discovery board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef __PERIPH_CONF_H
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#define __PERIPH_CONF_H
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TIM2
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (71U)
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#define TIMER_0_MAX_VALUE (0xffffffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
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#define TIMER_0_ISR isr_tim2
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#define TIMER_0_IRQ_CHAN TIM2_IRQn
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (3U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_2_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART1
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#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_0_CLK (CLOCK_CORECLOCK / 1) /* UART clock runs with 72MHz (F_CPU / 1) */
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#define UART_0_IRQ_CHAN USART1_IRQn
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#define UART_0_ISR isr_usart1
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/* UART 0 pin configuration */
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#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define UART_0_PORT GPIOA
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#define UART_0_TX_PIN 9
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#define UART_0_RX_PIN 10
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#define UART_0_AF 7
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/* UART 1 device configuration */
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#define UART_1_DEV USART2
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#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_1_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 36MHz (F_CPU / 2) */
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#define UART_1_IRQ_CHAN USART2_IRQn
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#define UART_1_ISR isr_usart2
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/* UART 1 pin configuration */
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#define UART_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
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#define UART_1_PORT GPIOD
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#define UART_1_TX_PIN 5
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#define UART_1_RX_PIN 6
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#define UART_1_AF 7
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/* UART 1 device configuration */
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#define UART_2_DEV USART3
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#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
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#define UART_2_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 36MHz (F_CPU / 2) */
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#define UART_2_IRQ_CHAN USART3_IRQn
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#define UART_2_ISR isr_usart3
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/* UART 1 pin configuration */
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#define UART_2_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
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#define UART_2_PORT GPIOD
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#define UART_2_TX_PIN 8
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#define UART_2_RX_PIN 9
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#define UART_2_AF 7
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/** @} */
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/**
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* @brief GPIO configuration
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* @{
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*/
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#define GPIO_NUMOF 12
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#define GPIO_0_EN 1
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#define GPIO_1_EN 1
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#define GPIO_2_EN 1
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#define GPIO_3_EN 1
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#define GPIO_4_EN 1
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#define GPIO_5_EN 1
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#define GPIO_6_EN 1
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#define GPIO_7_EN 1
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#define GPIO_8_EN 1
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#define GPIO_9_EN 1
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#define GPIO_10_EN 1
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#define GPIO_11_EN 1
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#define GPIO_IRQ_PRIO 1
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/* IRQ config */
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#define GPIO_IRQ_0 GPIO_11 /* alternatively GPIO_4 could be used here */
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#define GPIO_IRQ_1 GPIO_5
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#define GPIO_IRQ_2 GPIO_0
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#define GPIO_IRQ_3 GPIO_3
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#define GPIO_IRQ_4 GPIO_1
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#define GPIO_IRQ_5 GPIO_2
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#define GPIO_IRQ_6 (-1) /* not configured */
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#define GPIO_IRQ_7 (-1) /* not configured */
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#define GPIO_IRQ_8 (-1) /* not configured */
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#define GPIO_IRQ_9 (-1) /* not configured */
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#define GPIO_IRQ_10 (-1) /* not configured */
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#define GPIO_IRQ_11 GPIO_6
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#define GPIO_IRQ_12 GPIO_7
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#define GPIO_IRQ_13 GPIO_8
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#define GPIO_IRQ_14 GPIO_9
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#define GPIO_IRQ_15 GPIO_10
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/* GPIO channel 0 config */
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#define GPIO_0_PORT GPIOE /* LSM303DLHC -> DRDY */
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#define GPIO_0_PIN 2
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#define GPIO_0_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
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#define GPIO_0_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI2))
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#define GPIO_0_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PE)
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#define GPIO_0_IRQ EXTI2_TSC_IRQn
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/* GPIO channel 1 config */
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#define GPIO_1_PORT GPIOE /* LSM303DLHC -> INT1 */
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#define GPIO_1_PIN 4
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#define GPIO_1_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
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#define GPIO_1_EXTI_CFG1() (SYSCFG->EXTICR[1] &= ~(SYSCFG_EXTICR2_EXTI4))
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#define GPIO_1_EXTI_CFG2() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PE)
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#define GPIO_1_IRQ EXTI4_IRQn
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/* GPIO channel 2 config */
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#define GPIO_2_PORT GPIOE /* LSM303DLHC -> INT2 */
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#define GPIO_2_PIN 5
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#define GPIO_2_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
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#define GPIO_2_EXTI_CFG1() (SYSCFG->EXTICR[1] &= ~(SYSCFG_EXTICR2_EXTI5))
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#define GPIO_2_EXTI_CFG2() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PE)
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#define GPIO_2_IRQ EXTI9_5_IRQn
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/* GPIO channel 3 config */
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#define GPIO_3_PORT GPIOE /* L2GD20 -> CS */
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#define GPIO_3_PIN 3
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#define GPIO_3_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
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#define GPIO_3_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI3))
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#define GPIO_3_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PE)
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#define GPIO_3_IRQ EXTI3_IRQn
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/* GPIO channel 4 config */
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||||
#define GPIO_4_PORT GPIOE /* L2GD20 -> INT1 */
|
||||
#define GPIO_4_PIN 0
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||||
#define GPIO_4_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
|
||||
#define GPIO_4_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI0))
|
||||
#define GPIO_4_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PE)
|
||||
#define GPIO_4_IRQ EXTI0_IRQn
|
||||
/* GPIO channel 5 config */
|
||||
#define GPIO_5_PORT GPIOE /* L2GD20 -> INT2/DRDY */
|
||||
#define GPIO_5_PIN 1
|
||||
#define GPIO_5_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOEEN)
|
||||
#define GPIO_5_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI1))
|
||||
#define GPIO_5_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PE)
|
||||
#define GPIO_5_IRQ EXTI1_IRQn
|
||||
/* GPIO channel 6 config */
|
||||
#define GPIO_6_PORT GPIOB
|
||||
#define GPIO_6_PIN 11
|
||||
#define GPIO_6_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
|
||||
#define GPIO_6_EXTI_CFG1() (SYSCFG->EXTICR[2] &= ~(SYSCFG_EXTICR3_EXTI11))
|
||||
#define GPIO_6_EXTI_CFG2() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PB)
|
||||
#define GPIO_6_IRQ EXTI15_10_IRQn
|
||||
/* GPIO channel 7 config */
|
||||
#define GPIO_7_PORT GPIOB
|
||||
#define GPIO_7_PIN 12
|
||||
#define GPIO_7_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
|
||||
#define GPIO_7_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI12))
|
||||
#define GPIO_7_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PB)
|
||||
#define GPIO_7_IRQ EXTI15_10_IRQn
|
||||
/* GPIO channel 8 config */
|
||||
#define GPIO_8_PORT GPIOB
|
||||
#define GPIO_8_PIN 13
|
||||
#define GPIO_8_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
|
||||
#define GPIO_8_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI13))
|
||||
#define GPIO_8_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PB)
|
||||
#define GPIO_8_IRQ EXTI15_10_IRQn
|
||||
/* GPIO channel 9 config */
|
||||
#define GPIO_9_PORT GPIOB
|
||||
#define GPIO_9_PIN 14
|
||||
#define GPIO_9_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
|
||||
#define GPIO_9_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI14))
|
||||
#define GPIO_9_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI14_PB)
|
||||
#define GPIO_9_IRQ EXTI15_10_IRQn
|
||||
/* GPIO channel 10 config */
|
||||
#define GPIO_10_PORT GPIOB
|
||||
#define GPIO_10_PIN 15
|
||||
#define GPIO_10_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
|
||||
#define GPIO_10_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI15))
|
||||
#define GPIO_10_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI15_PB)
|
||||
#define GPIO_10_IRQ EXTI15_10_IRQn
|
||||
/* GPIO channel 11 config */
|
||||
#define GPIO_11_PORT GPIOA /* User button 1 */
|
||||
#define GPIO_11_PIN 0
|
||||
#define GPIO_11_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
|
||||
#define GPIO_11_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI0))
|
||||
#define GPIO_11_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
|
||||
#define GPIO_11_IRQ EXTI0_IRQn
|
||||
/** @} */
|
||||
|
||||
#endif /* __PERIPH_CONF_H */
|
||||
Loading…
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Reference in New Issue
Block a user