From 982f36cdb0460a24d08e6ec047040516b4eb557d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Dauphin?= Date: Wed, 17 Jan 2018 18:12:14 +0100 Subject: [PATCH] cpu/kinetis: add support of MK20D7 --- cpu/kinetis/include/cpu_conf_kinetis.h | 13 + cpu/kinetis/include/cpu_conf_kinetis_k.h | 16 + cpu/kinetis/include/vendor/MK20D7.h | 7801 ++++++++++++++++++++++ cpu/kinetis/kinetis-info.mk | 2 + 4 files changed, 7832 insertions(+) create mode 100644 cpu/kinetis/include/vendor/MK20D7.h diff --git a/cpu/kinetis/include/cpu_conf_kinetis.h b/cpu/kinetis/include/cpu_conf_kinetis.h index 135bdc9d09..0a7aee7262 100644 --- a/cpu/kinetis/include/cpu_conf_kinetis.h +++ b/cpu/kinetis/include/cpu_conf_kinetis.h @@ -128,6 +128,19 @@ extern "C" #endif /* KINETIS_RNGA */ /** @} */ +/** + * @name MK20D7 Compatibility layer + * @{ + */ +#if defined(MK20D7_H_) +#define LLWU_IRQn LLW_IRQn +#define LPTMR0_IRQn LPTimer_IRQn +#define PIT_TCTRL_CHN_MASK (0x4u) +#define PIT_TCTRL_CHN_SHIFT (2) +#endif /* MK20D7_H_ */ +/** @} */ + + #ifdef __cplusplus } #endif diff --git a/cpu/kinetis/include/cpu_conf_kinetis_k.h b/cpu/kinetis/include/cpu_conf_kinetis_k.h index 9a3ac1aa27..58de7ee115 100644 --- a/cpu/kinetis/include/cpu_conf_kinetis_k.h +++ b/cpu/kinetis/include/cpu_conf_kinetis_k.h @@ -70,6 +70,22 @@ defined(CPU_MODEL_MK22FX512AVMD12) #include "vendor/MK22FA12.h" #endif +#elif (KINETIS_SUBFAMILY == 0) +#if defined(CPU_MODEL_MK20DX64VLH7) || \ + defined(CPU_MODEL_MK20DX128VLH7) || \ + defined(CPU_MODEL_MK20DX256VLH7) || \ + defined(CPU_MODEL_MK20DX64VLK7) || \ + defined(CPU_MODEL_MK20DX128VLK7) || \ + defined(CPU_MODEL_MK20DX256VLK7) || \ + defined(CPU_MODEL_MK20DX128VLL7) || \ + defined(CPU_MODEL_MK20DX256VLL7) || \ + defined(CPU_MODEL_MK20DX64VMB7) || \ + defined(CPU_MODEL_MK20DX128VMB7) || \ + defined(CPU_MODEL_MK20DX256VMB7) || \ + defined(CPU_MODEL_MK20DX128VML7) || \ + defined(CPU_MODEL_MK20DX256VML7) +#include "vendor/MK20D7.h" +#endif #endif /* (KINETIS_SUBFAMILY == y) */ #elif (KINETIS_FAMILY == 6) #if (KINETIS_SUBFAMILY == 0) diff --git a/cpu/kinetis/include/vendor/MK20D7.h b/cpu/kinetis/include/vendor/MK20D7.h new file mode 100644 index 0000000000..10a880e111 --- /dev/null +++ b/cpu/kinetis/include/vendor/MK20D7.h @@ -0,0 +1,7801 @@ +/* +** ################################################################### +** Processors: MK20DX64VLH7 +** MK20DX128VLH7 +** MK20DX256VLH7 +** MK20DX64VLK7 +** MK20DX128VLK7 +** MK20DX256VLK7 +** MK20DX128VLL7 +** MK20DX256VLL7 +** MK20DX64VMB7 +** MK20DX128VMB7 +** MK20DX256VMB7 +** MK20DX128VML7 +** MK20DX256VML7 +** +** Compilers: ARM Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: K20P144M72SF1RM Rev. 0, Nov 2011 +** Version: rev. 1.3, 2013-06-24 +** +** Abstract: +** CMSIS Peripheral Access Layer for MK20D7 +** +** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2012-01-15) +** Initial public version. +** - rev. 1.1 (2012-04-13) +** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR. +** Added new #define symbols _BASE_PTRS. +** - rev. 1.2 (2013-04-05) +** Changed start of doxygen comment. +** - rev. 1.3 (2013-06-24) +** NV_FOPT register - NMI_DIS bit added. +** +** ################################################################### +*/ + +/*! + * @file MK20D7.h + * @version 1.3 + * @date 2013-06-24 + * @brief CMSIS Peripheral Access Layer for MK20D7 + * + * CMSIS Peripheral Access Layer for MK20D7 + */ + +#if !defined(MK20D7_H_) +#define MK20D7_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0003u + +/** + * @brief Macro to calculate address of an aliased word in the peripheral + * bitband area for a peripheral register and bit (bit band region 0x40000000 to + * 0x400FFFFF). + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Address of the aliased word in the peripheral bitband area. + */ +#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 32bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 16bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 8bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 111 /**< Number of interrupts in the Vector table */ + +/** Interrupt Number Definitions */ +typedef enum IRQn { + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ + DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ + DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ + DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ + DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ + DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ + DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ + DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ + DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ + DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ + DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ + DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ + DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ + DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ + DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ + DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ + DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ + MCM_IRQn = 17, /**< Normal interrupt */ + FTFL_IRQn = 18, /**< FTFL Interrupt */ + Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ + LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ + LLW_IRQn = 21, /**< Low Leakage Wakeup */ + Watchdog_IRQn = 22, /**< WDOG Interrupt */ + Reserved39_IRQn = 23, /**< Reserved Interrupt 39 */ + I2C0_IRQn = 24, /**< I2C0 interrupt */ + I2C1_IRQn = 25, /**< I2C1 interrupt */ + SPI0_IRQn = 26, /**< SPI0 Interrupt */ + SPI1_IRQn = 27, /**< SPI1 Interrupt */ + Reserved44_IRQn = 28, /**< Reserved interrupt 44 */ + CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd Message Buffers Interrupt */ + CAN0_Bus_Off_IRQn = 30, /**< CAN0 Bus Off Interrupt */ + CAN0_Error_IRQn = 31, /**< CAN0 Error Interrupt */ + CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx Warning Interrupt */ + CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx Warning Interrupt */ + CAN0_Wake_Up_IRQn = 34, /**< CAN0 Wake Up Interrupt */ + I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */ + I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */ + Reserved53_IRQn = 37, /**< Reserved interrupt 53 */ + Reserved54_IRQn = 38, /**< Reserved interrupt 54 */ + Reserved55_IRQn = 39, /**< Reserved interrupt 55 */ + Reserved56_IRQn = 40, /**< Reserved interrupt 56 */ + Reserved57_IRQn = 41, /**< Reserved interrupt 57 */ + Reserved58_IRQn = 42, /**< Reserved interrupt 58 */ + Reserved59_IRQn = 43, /**< Reserved interrupt 59 */ + UART0_LON_IRQn = 44, /**< UART0 LON interrupt */ + UART0_RX_TX_IRQn = 45, /**< UART0 Receive/Transmit interrupt */ + UART0_ERR_IRQn = 46, /**< UART0 Error interrupt */ + UART1_RX_TX_IRQn = 47, /**< UART1 Receive/Transmit interrupt */ + UART1_ERR_IRQn = 48, /**< UART1 Error interrupt */ + UART2_RX_TX_IRQn = 49, /**< UART2 Receive/Transmit interrupt */ + UART2_ERR_IRQn = 50, /**< UART2 Error interrupt */ + UART3_RX_TX_IRQn = 51, /**< UART3 Receive/Transmit interrupt */ + UART3_ERR_IRQn = 52, /**< UART3 Error interrupt */ + UART4_RX_TX_IRQn = 53, /**< UART4 Receive/Transmit interrupt */ + UART4_ERR_IRQn = 54, /**< UART4 Error interrupt */ + Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ + Reserved72_IRQn = 56, /**< Reserved interrupt 72 */ + ADC0_IRQn = 57, /**< ADC0 interrupt */ + ADC1_IRQn = 58, /**< ADC1 interrupt */ + CMP0_IRQn = 59, /**< CMP0 interrupt */ + CMP1_IRQn = 60, /**< CMP1 interrupt */ + CMP2_IRQn = 61, /**< CMP2 interrupt */ + FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */ + FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */ + FTM2_IRQn = 64, /**< FTM2 fault, overflow and channels interrupt */ + CMT_IRQn = 65, /**< CMT interrupt */ + RTC_IRQn = 66, /**< RTC interrupt */ + RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */ + PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */ + PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */ + PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */ + PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */ + PDB0_IRQn = 72, /**< PDB0 Interrupt */ + USB0_IRQn = 73, /**< USB0 interrupt */ + USBDCD_IRQn = 74, /**< USBDCD Interrupt */ + Reserved91_IRQn = 75, /**< Reserved interrupt 91 */ + Reserved92_IRQn = 76, /**< Reserved interrupt 92 */ + Reserved93_IRQn = 77, /**< Reserved interrupt 93 */ + Reserved94_IRQn = 78, /**< Reserved interrupt 94 */ + Reserved95_IRQn = 79, /**< Reserved interrupt 95 */ + Reserved96_IRQn = 80, /**< Reserved interrupt 96 */ + DAC0_IRQn = 81, /**< DAC0 interrupt */ + Reserved98_IRQn = 82, /**< Reserved interrupt 98 */ + TSI0_IRQn = 83, /**< TSI0 Interrupt */ + MCG_IRQn = 84, /**< MCG Interrupt */ + LPTimer_IRQn = 85, /**< LPTimer interrupt */ + Reserved102_IRQn = 86, /**< Reserved interrupt 102 */ + PORTA_IRQn = 87, /**< Port A interrupt */ + PORTB_IRQn = 88, /**< Port B interrupt */ + PORTC_IRQn = 89, /**< Port C interrupt */ + PORTD_IRQn = 90, /**< Port D interrupt */ + PORTE_IRQn = 91, /**< Port E interrupt */ + Reserved108_IRQn = 92, /**< Reserved interrupt 108 */ + Reserved109_IRQn = 93, /**< Reserved interrupt 109 */ + SWI_IRQn = 94 /**< Software interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ + __IO uint32_t PGA; /**< ADC PGA register, offset: 0x50 */ + __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0 +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<