Merge pull request #3170 from A-Paul/sam3x8e-periph-pwm
cpu/sam3x8e: Add pwm implementation
This commit is contained in:
Peter Kietzmann
commit
98312452ce
@ -1,6 +1,7 @@
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FEATURES_PROVIDED += cpp
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_random
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FEATURES_MCU_GROUP = cortex_m3_1
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@ -15,6 +15,7 @@
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
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* @author Andreas "Paul" Pauli <andreas.pauli@haw-hamburg.de>
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*/
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#ifndef __PERIPH_CONF_H
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@ -342,6 +343,37 @@ extern "C" {
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#define GPIO_B21_MAP 31
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF (1U)
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#define PWM_0_EN (1)
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#define PWM_MAX_VALUE (0xffff)
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#define PWM_MAX_CHANNELS (4U)
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/* PWM_0 configuration */
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#define PWM_0_DEV PWM
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#define PWM_0_PID ID_PWM
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#define PWM_0_CHANNELS (4U)
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#define PWM_0_DEV_CH0 (&(PWM_0_DEV->PWM_CH_NUM[4]))
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#define PWM_0_ENA_CH0 PWM_ENA_CHID4
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#define PWM_0_PORT_CH0 PIOC
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#define PWM_0_PIN_CH0 PIO_PC21B_PWML4
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#define PWM_0_DEV_CH1 (&(PWM_0_DEV->PWM_CH_NUM[5]))
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#define PWM_0_ENA_CH1 PWM_ENA_CHID5
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#define PWM_0_PORT_CH1 PIOC
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#define PWM_0_PIN_CH1 PIO_PC22B_PWML5
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#define PWM_0_DEV_CH2 (&(PWM_0_DEV->PWM_CH_NUM[6]))
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#define PWM_0_ENA_CH2 PWM_ENA_CHID6
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#define PWM_0_PORT_CH2 PIOC
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#define PWM_0_PIN_CH2 PIO_PC23B_PWML6
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#define PWM_0_DEV_CH3 (&(PWM_0_DEV->PWM_CH_NUM[7]))
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#define PWM_0_ENA_CH3 PWM_ENA_CHID7
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#define PWM_0_PORT_CH3 PIOC
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#define PWM_0_PIN_CH3 PIO_PC24B_PWML7
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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291
cpu/sam3x8e/periph/pwm.c
Normal file
291
cpu/sam3x8e/periph/pwm.c
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@ -0,0 +1,291 @@
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/*
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_sam3x8e
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* @{
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*
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* @file
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* @brief CPU specific low-level PWM driver implementation for the SAM3X8E
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*
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* @author Andreas "Paul" Pauli <andreas.pauli@haw-hamburg.de>
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*
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* @}
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*/
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#include <stdint.h>
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#include "board.h"
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#include "periph/pwm.h"
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/*
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* guard file in case no PWM device is defined,
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*/
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#if PWM_NUMOF && PWM_0_EN
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#define ERR_INIT_MODE (-1)
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#define ERR_INIT_BWTH (-2)
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#define ERR_SET_CHAN (-1)
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#define MCK_DIV_LB_MAX (10U)
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int pwm_init(pwm_t dev, pwm_mode_t mode,
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unsigned int frequency,
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unsigned int resolution)
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{
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int32_t retval = ERR_INIT_MODE; /* Worst/First case */
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uint32_t pwm_clk = 0; /* Desired/real pwm_clock */
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uint32_t diva = 1; /* Candidate for 8bit divider */
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uint32_t prea = 0; /* Candidate for clock select */
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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break;
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#endif
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default:
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return ERR_INIT_MODE;
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}
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/*
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* Mode check.
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* Only PW_LEFT -which is hw default- supported for now.
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*/
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switch (mode) {
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case PWM_LEFT:
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break;
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case PWM_RIGHT:
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case PWM_CENTER:
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default:
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return ERR_INIT_MODE;
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}
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/* Should check if "|log_2 frequency|+|log_2 resolution| <= 32" */
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pwm_clk = frequency * resolution;
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/*
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* The pwm provides 11 prescaled clocks with (MCK/2^prea | prea=[0,10])
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* and a divider (diva) with a denominator range [1,255] in line.
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*/
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if (F_CPU < pwm_clk) { /* Have to cut down resulting frequency. */
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frequency = F_CPU / resolution;
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}
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else { /* Estimate prescaler and divider. */
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diva = F_CPU / pwm_clk;
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while ((prea < MCK_DIV_LB_MAX) && (~0xff & diva)) {
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prea = prea + 1;
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diva = diva >> 1;
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}
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frequency = F_CPU / ((resolution * diva) << prea);
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}
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retval = frequency;
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/* Activate PWM block by enabling it's clock. */
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PMC->PMC_PCER1 = PMC_PCER1_PID36;
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/* Unlock User Interface */
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PWM_0_DEV->PWM_WPCR = PWM_ENA_CHID0;
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/* Disable all channels to allow CPRD updates. */
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PWM_0_DEV->PWM_DIS = 0xff;
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/* Step 2. Configure clock generator */
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PWM_0_DEV->PWM_CLK = PWM_CLK_PREA(prea) | PWM_CLK_DIVA(diva) |
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(~(PWM_CLK_PREA_Msk | PWM_CLK_DIVA_Msk) &
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PWM_0_DEV->PWM_CLK);
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/* +++++++++++ Configure and init channels +++++++++++++++ */
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/* Set clock source, resolution, duty-cycle and enable */
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#if PWM_0_CHANNELS > 0
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PWM_0_DEV_CH0->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH0->PWM_CPRD = resolution - 1;
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PWM_0_DEV_CH0->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH0;
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#endif
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#if PWM_0_CHANNELS > 1
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PWM_0_DEV_CH1->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH1->PWM_CPRD = resolution - 1;
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PWM_0_DEV_CH1->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH1;
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#endif
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#if PWM_0_CHANNELS > 2
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PWM_0_DEV_CH2->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH2->PWM_CPRD = resolution - 1;
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PWM_0_DEV_CH2->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH2;
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#endif
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#if PWM_0_CHANNELS > 3
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PWM_0_DEV_CH3->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH3->PWM_CPRD = resolution - 1;
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PWM_0_DEV_CH3->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH3;
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#endif
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/* +++++++++++ Configure and init channels ready++++++++++ */
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/*
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* Disable GPIO and set peripheral A/B ("0/1") for pwm channel pins.
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*/
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#if PWM_0_CHANNELS > 0
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PWM_0_PORT_CH0->PIO_PDR |= PWM_0_PIN_CH0;
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PWM_0_PORT_CH0->PIO_ABSR |= PWM_0_PIN_CH0;
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#endif
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#if PWM_0_CHANNELS > 1
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PWM_0_PORT_CH1->PIO_PDR |= PWM_0_PIN_CH1;
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PWM_0_PORT_CH1->PIO_ABSR |= PWM_0_PIN_CH1;
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#endif
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#if PWM_0_CHANNELS > 2
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PWM_0_PORT_CH2->PIO_PDR |= PWM_0_PIN_CH2;
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PWM_0_PORT_CH2->PIO_ABSR |= PWM_0_PIN_CH2;
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#endif
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#if PWM_0_CHANNELS > 3
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PWM_0_PORT_CH3->PIO_PDR |= PWM_0_PIN_CH3;
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PWM_0_PORT_CH3->PIO_ABSR |= PWM_0_PIN_CH3;
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#endif
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return retval;
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}
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/*
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* Update duty-cycle in channel with value.
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* If value is larger than resolution set by pwm_init() it is cropped.
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*/
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int pwm_set(pwm_t dev, int channel, unsigned int value)
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{
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int retval = ERR_SET_CHAN; /* Worst case */
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uint32_t period = 0; /* Store pwm period */
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PwmCh_num *chan = (void *)0; /* Addressed channel. */
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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break;
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#endif
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default:
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return ERR_SET_CHAN;
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}
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switch (channel) {
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#if PWM_0_CHANNELS > 0
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case 0:
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chan = PWM_0_DEV_CH0;
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break;
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#endif
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#if PWM_0_CHANNELS > 1
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case 1:
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chan = PWM_0_DEV_CH1;
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break;
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#endif
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#if PWM_0_CHANNELS > 2
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case 2:
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chan = PWM_0_DEV_CH2;
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break;
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#endif
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#if PWM_0_CHANNELS > 3
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case 3:
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chan = PWM_0_DEV_CH3;
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break;
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#endif
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default:
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retval = ERR_SET_CHAN;
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}
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if (chan) {
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period = chan->PWM_CPRD & PWM_CPRD_CPRD_Msk;
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if (value < period) {
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chan->PWM_CDTYUPD = value;
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}
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else { /* Value Out of range. Clip silent as required by interface. */
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chan->PWM_CDTYUPD = period;
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}
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retval = 0;
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}
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return retval;
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}
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/*
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* Continue operation.
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*/
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void pwm_start(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PMC->PMC_PCER1 |= PMC_PCER1_PID36;
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break;
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#endif
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}
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}
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/*
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* Stop operation and set output to 0.
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*/
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void pwm_stop(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PMC->PMC_PCDR1 |= PMC_PCDR1_PID36;
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break;
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#endif
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}
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}
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/*
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* The device is reactivated by by clocking the device block.
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* Operation continues where it has been stopped by poweroff.
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*/
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void pwm_poweron(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PMC->PMC_PCER1 |= PMC_PCER1_PID36;
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break;
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#endif
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}
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}
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/*
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* The device is set to power saving mode by disabling the clock.
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*/
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void pwm_poweroff(pwm_t dev)
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{
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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PMC->PMC_PCDR1 |= PMC_PCDR1_PID36;
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break;
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#endif
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}
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}
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#endif /* PWM_NUMOF */
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