diff --git a/boards/stm32f4discovery/Makefile b/boards/stm32f4discovery/Makefile new file mode 100644 index 0000000000..37891de8e6 --- /dev/null +++ b/boards/stm32f4discovery/Makefile @@ -0,0 +1,4 @@ +# tell the Makefile.base which module to build +MODULE = $(BOARD)_base + +include $(RIOTBASE)/Makefile.base diff --git a/boards/stm32f4discovery/Makefile.include b/boards/stm32f4discovery/Makefile.include new file mode 100644 index 0000000000..7306ca20cb --- /dev/null +++ b/boards/stm32f4discovery/Makefile.include @@ -0,0 +1,47 @@ +# define the cpu used by the stm32f4-discovery board +export CPU = stm32f4 +export CPU_MODEL = stm32f407vg + +#define the default port depending on the host OS +OS := $(shell uname) +ifeq ($(OS),Linux) + PORT ?= /dev/ttyUSB0 +else ifeq ($(OS),Darwin) + PORT ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1) +else + $(info CAUTION: No flash tool for your host system found!) + # TODO: add support for windows as host platform +endif +export PORT + +# define tools used for building the project +export PREFIX = arm-none-eabi- +export CC = $(PREFIX)gcc +export AR = $(PREFIX)ar +export AS = $(PREFIX)as +export LINK = $(PREFIX)gcc +export SIZE = $(PREFIX)size +export OBJCOPY = $(PREFIX)objcopy +export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm.py +export FLASHER = st-flash +export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh + +# define build specific options +CPU_USAGE = -mcpu=cortex-m4 +FPU_USAGE = -mfloat-abi=hard -mfpu=fpv4-sp-d16 +export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles +export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin +export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian +export LINKFLAGS += -g3 -ggdb -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles +export LINKFLAGS += -T$(LINKERSCRIPT) +export OFLAGS = -O binary +export FFLAGS = write bin/$(BOARD)/$(APPLICATION).hex 0x8000000 +export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(BINDIR)/$(APPLICATION).elf + +# use newLib nano-specs if available +ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null + * + * @} + */ + +#include "board.h" + +static void leds_init(void); + +void board_init(void) +{ + /* initialize the boards LEDs, this is done first for debugging purposes */ + leds_init(); + + /* initialize the CPU */ + cpu_init(); +} + +/** + * @brief Initialize the boards on-board LEDs (LD3 and LD4) + * + * The LED initialization is hard-coded in this function. As the LEDs are soldered + * onto the board they are fixed to their CPU pins. + * + * The LEDs are connected to the following pins: + * - LD3: PD13 + * - LD4: PD12 + * - LD5: PD14 + * - LD6: PD15 + */ +static void leds_init(void) +{ + /* enable clock for port GPIOD */ + RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; + + /* configure pins as general outputs */ + LED_PORT->MODER &= ~(0xff000000); + LED_PORT->MODER |= 0x55000000; + /* set output speed high-speed */ + LED_PORT->OSPEEDR |= 0xff000000; + /* set output type to push-pull */ + LED_PORT->OTYPER &= ~(0xf000); + /* disable pull resistors */ + LED_PORT->PUPDR &= ~(0xff000000); + + /* turn all LEDs off */ + LED_PORT->BSRRH = 0xf000; +} diff --git a/boards/stm32f4discovery/dist/debug.sh b/boards/stm32f4discovery/dist/debug.sh new file mode 100755 index 0000000000..1a0c4b0cd4 --- /dev/null +++ b/boards/stm32f4discovery/dist/debug.sh @@ -0,0 +1,4 @@ +#!/bin/sh + +echo "Debugging $1" +arm-none-eabi-gdb -tui -command=$1 $2 diff --git a/boards/stm32f4discovery/dist/gdb.conf b/boards/stm32f4discovery/dist/gdb.conf new file mode 100644 index 0000000000..7257c72805 --- /dev/null +++ b/boards/stm32f4discovery/dist/gdb.conf @@ -0,0 +1 @@ +tar extended-remote :4242 diff --git a/boards/stm32f4discovery/include/board.h b/boards/stm32f4discovery/include/board.h new file mode 100644 index 0000000000..e40813bc2e --- /dev/null +++ b/boards/stm32f4discovery/include/board.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup board_stm32f4discovery STM32F4Discovery + * @ingroup boards + * @brief Board specific files for the STM32F4Discovery board + * @{ + * + * @file + * @brief Board specific definitions for the STM32F4Discovery evaluation board + * + * @author Hauke Petersen + */ + +#ifndef __BOARD_H +#define __BOARD_H + +#include "cpu.h" +#include "periph_conf.h" + +/** + * Define the nominal CPU core clock in this board + */ +#define F_CPU CLOCK_CORECLOCK + +/** + * @name Assign the hardware timer + */ +#define HW_TIMER TIMER_0 + +/** + * @name Define UART device and baudrate for stdio + * @{ + */ +#define STDIO UART_0 +#define STDIO_BAUDRATE (115200U) +/** @} */ + +/** + * @name LED pin definitions + * @{ + */ +#define LED_PORT GPIOD +#define LD3_PIN (1 << 13) +#define LD4_PIN (1 << 12) +#define LD5_PIN (1 << 14) +#define LD6_PIN (1 << 15) +/** @} */ + +/** + * @name Macros for controlling the on-board LEDs. + * @{ + */ +#define LD3_ON (LED_PORT->BSRRL = LD3_PIN) +#define LD3_OFF (LED_PORT->BSRRH = LD3_PIN) +#define LD3_TOGGLE (LED_PORT->ODR ^= LD3_PIN) +#define LD4_ON (LED_PORT->BSRRL = LD4_PIN) +#define LD4_OFF (LED_PORT->BSRRH = LD4_PIN) +#define LD4_TOGGLE (LED_PORT->ODR ^= LD4_PIN) +#define LD5_ON (LED_PORT->BSRRL = LD5_PIN) +#define LD5_OFF (LED_PORT->BSRRH = LD5_PIN) +#define LD5_TOGGLE (LED_PORT->ODR ^= LD5_PIN) +#define LD6_ON (LED_PORT->BSRRL = LD6_PIN) +#define LD6_OFF (LED_PORT->BSRRH = LD6_PIN) +#define LD6_TOGGLE (LED_PORT->ODR ^= LD6_PIN) + +/* for compatability to other boards */ +#define LED_GREEN_ON LD4_ON +#define LED_GREEN_OFF LD4_OFF +#define LED_GREEN_TOGGLE LD4_TOGGLE +#define LED_RED_ON LD5_ON +#define LED_RED_OFF LD5_OFF +#define LED_RED_TOGGLE LD5_TOGGLE +/** @} */ + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +#endif /** __BOARD_H */ +/** @} */ diff --git a/boards/stm32f4discovery/include/periph_conf.h b/boards/stm32f4discovery/include/periph_conf.h new file mode 100644 index 0000000000..bf41fe09cc --- /dev/null +++ b/boards/stm32f4discovery/include/periph_conf.h @@ -0,0 +1,386 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup board_stm32f4discovery + * @{ + * + * @file + * @name Peripheral MCU configuration for the STM32F4discovery board + * + * @author Hauke Petersen + */ + +#ifndef __PERIPH_CONF_H +#define __PERIPH_CONF_H + +/** + * @name Clock system configuration + * @{ + */ +#define CLOCK_HSE (8000000U) /* external oscillator */ +#define CLOCK_CORECLOCK (168000000U) /* desired core clock frequency */ + +/* the actual PLL values are automatically generated */ +#define CLOCK_PLL_M (CLOCK_HSE / 1000000) +#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2) +#define CLOCK_PLL_P (2U) +#define CLOCK_PLL_Q (CLOCK_PLL_N / 48) +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 +#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS +/** @} */ + + +/** + * @name Timer configuration + * @{ + */ +#define TIMER_NUMOF (2U) +#define TIMER_0_EN 1 +#define TIMER_1_EN 1 +#define TIMER_IRQ_PRIO 1 + +/* Timer 0 configuration */ +#define TIMER_0_DEV TIM2 +#define TIMER_0_CHANNELS 4 +#define TIMER_0_PRESCALER (83U) +#define TIMER_0_MAX_VALUE (0xffffffff) +#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN) +#define TIMER_0_ISR isr_tim2 +#define TIMER_0_IRQ_CHAN TIM2_IRQn + +/* Timer 1 configuration */ +#define TIMER_1_DEV TIM5 +#define TIMER_1_CHANNELS 4 +#define TIMER_1_PRESCALER (83U) +#define TIMER_1_MAX_VALUE (0xffffffff) +#define TIMER_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN) +#define TIMER_1_ISR isr_tim5 +#define TIMER_1_IRQ_CHAN TIM5_IRQn +/** @} */ + + +/** + * @name UART configuration + * @{ + */ +#define UART_NUMOF (2U) +#define UART_0_EN 1 +#define UART_1_EN 1 +#define UART_IRQ_PRIO 1 +#define UART_CLK (14000000U) /* UART clock runs with 14MHz */ + +/* UART 0 device configuration */ +#define UART_0_DEV USART2 +#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN) +#define UART_0_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */ +#define UART_0_IRQ_CHAN USART2_IRQn +#define UART_0_ISR isr_usart2 +/* UART 0 pin configuration */ +#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) +#define UART_0_PORT GPIOA +#define UART_0_TX_PIN 2 +#define UART_0_RX_PIN 3 +#define UART_0_AF 7 + +/* UART 1 device configuration */ +#define UART_1_DEV USART3 +#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN) +#define UART_1_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */ +#define UART_1_IRQ_CHAN USART3_IRQn +#define UART_1_ISR isr_usart3 +/* UART 1 pin configuration */ +#define UART_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN) +#define UART_1_PORT GPIOD +#define UART_1_TX_PIN 8 +#define UART_1_RX_PIN 9 +#define UART_1_AF 7 +/** @} */ + + +/** + * @name ADC configuration + * @{ + */ +#define ADC_NUMOF (0U) +#define ADC_0_EN 0 +#define ADC_1_EN 0 + +/* ADC 0 configuration */ +#define ADC_0_DEV ADC1 /* TODO !!!!!!! */ +#define ADC_0_SAMPLE_TIMER +/* ADC 0 channel 0 pin config */ +#define ADC_0_C0_PORT +#define ADC_0_C0_PIN +#define ADC_0_C0_CLKEN() +#define ADC_0_C0_AFCFG() +/* ADC 0 channel 1 pin config */ +#define ADC_0_C1_PORT +#define ADC_0_C1_PIN +#define ADC_0_C1_CLKEN() +#define ADC_0_C1_AFCFG() +/* ADC 0 channel 2 pin config */ +#define ADC_0_C2_PORT +#define ADC_0_C2_PIN +#define ADC_0_C2_CLKEN() +#define ADC_0_C2_AFCFG() +/* ADC 0 channel 3 pin config */ +#define ADC_0_C3_PORT +#define ADC_0_C3_PIN +#define ADC_0_C3_CLKEN() +#define ADC_0_C3_AFCFG() + +/* ADC 0 configuration */ +#define ADC_1_DEV ADC2 /* TODO !!!!!!! */ +#define ADC_1_SAMPLE_TIMER +/* ADC 0 channel 0 pin config */ +#define ADC_1_C0_PORT +#define ADC_1_C0_PIN +#define ADC_1_C0_CLKEN() +#define ADC_1_C0_AFCFG() +/* ADC 0 channel 1 pin config */ +#define ADC_1_C1_PORT +#define ADC_1_C1_PIN +#define ADC_1_C1_CLKEN() +#define ADC_1_C1_AFCFG() +/* ADC 0 channel 2 pin config */ +#define ADC_1_C2_PORT +#define ADC_1_C2_PIN +#define ADC_1_C2_CLKEN() +#define ADC_1_C2_AFCFG() +/* ADC 0 channel 3 pin config */ +#define ADC_1_C3_PORT +#define ADC_1_C3_PIN +#define ADC_1_C3_CLKEN() +#define ADC_1_C3_AFCFG() +/** @} */ + + +/** + * @name PWM configuration + * @{ + */ +#define PWM_NUMOF (0U) /* TODO !!!!!!! */ +#define PWM_0_EN 0 +#define PWM_1_EN 0 + +/* PWM 0 device configuration */ +#define PWM_0_DEV TIM1 +#define PWM_0_CHANNELS 4 +/* PWM 0 pin configuration */ +#define PWM_0_PORT +#define PWM_0_PINS +#define PWM_0_PORT_CLKEN() +#define PWM_0_CH1_AFCFG() +#define PWM_0_CH2_AFCFG() +#define PWM_0_CH3_AFCFG() +#define PWM_0_CH4_AFCFG() + +/* PWM 1 device configuration */ +#define PWM_1_DEV TIM3 +#define PWM_1_CHANNELS 4 +/* PWM 1 pin configuration */ +#define PWM_1_PORT +#define PWM_1_PINS +#define PWM_1_PORT_CLKEN() +#define PWM_1_CH1_AFCFG() +#define PWM_1_CH2_AFCFG() +#define PWM_1_CH3_AFCFG() +#define PWM_1_CH4_AFCFG() +/** @} */ + + +/** + * @name SPI configuration + * @{ + */ +#define SPI_NUMOF (0U) /* TODO !!!!!!! */ +#define SPI_0_EN 0 +#define SPI_1_EN 0 + +/* SPI 0 device config */ +#define SPI_0_DEV +#define SPI_0_CLKEN() +#define SPI_0_IRQ +#define SPI_0_IRQ_HANDLER +#define SPI_0_IRQ_PRIO +/* SPI 1 pin configuration */ +#define SPI_0_PORT +#define SPI_0_PINS +#define SPI_1_PORT_CLKEN() +#define SPI_1_SCK_AFCFG() +#define SPI_1_MISO_AFCFG() +#define SPI_1_MOSI_AFCFG() + +/* SPI 1 device config */ +#define SPI_1_DEV +#define SPI_1_CLKEN() +#define SPI_1_IRQ +#define SPI_1_IRQ_HANDLER +#define SPI_1_IRQ_PRIO +/* SPI 1 pin configuration */ +#define SPI_1_PORT +#define SPI_1_PINS +#define SPI_1_PORT_CLKEN() +#define SPI_1_SCK_AFCFG() +#define SPI_1_MISO_AFCFG() +#define SPI_1_MOSI_AFCFG() +/** @} */ + + +/** + * @name I2C configuration + * @{ + */ +#define I2C_NUMOF (0U) /* TODO !!!!!!! */ +#define I2C_0_EN 0 +#define I2C_0_EN 0 + +/* SPI 0 device configuration */ +#define I2C_0_DEV +#define I2C_0_CLKEN() +#define I2C_0_ISR +#define I2C_0_IRQ +#define I2C_0_IRQ_PRIO +/* SPI 0 pin configuration */ +#define I2C_0_PORT +#define I2C_0_PINS +#define I2C_0_PORT_CLKEN() +#define I2C_0_SCL_AFCFG() +#define I2C_0_SDA_AFCFG() + +/* SPI 1 device configuration */ +#define I2C_1_DEV +#define I2C_1_CLKEN() +#define I2C_1_ISR +#define I2C_1_IRQ +#define I2C_1_IRQ_PRIO +/* SPI 1 pin configuration */ +#define I2C_1_PORT +#define I2C_1_PINS +#define I2C_1_PORT_CLKEN() +#define I2C_1_SCL_AFCFG() +#define I2C_1_SDA_AFCFG() +/** @} */ + + +/** + * @name GPIO configuration + * @{ + */ +#define GPIO_NUMOF 12 +#define GPIO_0_EN 1 +#define GPIO_1_EN 1 +#define GPIO_2_EN 1 +#define GPIO_3_EN 1 +#define GPIO_4_EN 1 +#define GPIO_5_EN 1 +#define GPIO_6_EN 1 +#define GPIO_7_EN 1 +#define GPIO_8_EN 1 +#define GPIO_9_EN 1 +#define GPIO_10_EN 1 +#define GPIO_11_EN 1 +#define GPIO_IRQ_PRIO 1 + +/* IRQ config */ +#define GPIO_IRQ_0 GPIO_0 /* alternatively GPIO_1 could be used here */ +#define GPIO_IRQ_1 GPIO_2 +#define GPIO_IRQ_2 GPIO_3 +#define GPIO_IRQ_3 GPIO_4 +#define GPIO_IRQ_4 GPIO_5 +#define GPIO_IRQ_5 GPIO_6 +#define GPIO_IRQ_6 GPIO_7 +#define GPIO_IRQ_7 GPIO_8 +#define GPIO_IRQ_8 GPIO_9 +#define GPIO_IRQ_9 GPIO_10 +#define GPIO_IRQ_10 GPIO_11 +#define GPIO_IRQ_11 -1/* not configured */ +#define GPIO_IRQ_12 -1/* not configured */ +#define GPIO_IRQ_13 -1/* not configured */ +#define GPIO_IRQ_14 -1/* not configured */ +#define GPIO_IRQ_15 -1/* not configured */ + +/* GPIO channel 0 config */ +#define GPIO_0_PORT GPIOA /* Used for user button 1 */ +#define GPIO_0_PIN 0 +#define GPIO_0_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) +#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA) +#define GPIO_0_IRQ EXTI0_IRQn +/* GPIO channel 1 config */ +#define GPIO_1_PORT GPIOE /* LIS302DL INT1 */ +#define GPIO_1_PIN 0 +#define GPIO_1_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN) +#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PE) +#define GPIO_1_IRQ EXTI0_IRQn +/* GPIO channel 2 config */ +#define GPIO_2_PORT GPIOE /* LIS302DL INT2 */ +#define GPIO_2_PIN 1 +#define GPIO_2_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN) +#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PE) +#define GPIO_2_IRQ EXTI1_IRQn +/* GPIO channel 3 config */ +#define GPIO_3_PORT GPIOE +#define GPIO_3_PIN 2 +#define GPIO_3_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN) +#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PE) +#define GPIO_3_IRQ EXTI2_IRQn +/* GPIO channel 4 config */ +#define GPIO_4_PORT GPIOE /* LIS302DL CS */ +#define GPIO_4_PIN 3 +#define GPIO_4_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN) +#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PE) +#define GPIO_4_IRQ EXTI3_IRQn +/* GPIO channel 5 config */ +#define GPIO_5_PORT GPIOD /* CS43L22 RESET */ +#define GPIO_5_PIN 4 +#define GPIO_5_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN) +#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PD) +#define GPIO_5_IRQ EXTI4_IRQn +/* GPIO channel 6 config */ +#define GPIO_6_PORT GPIOD /* LD8 */ +#define GPIO_6_PIN 5 +#define GPIO_6_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN) +#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PD) +#define GPIO_6_IRQ EXTI9_5_IRQn +/* GPIO channel 7 config */ +#define GPIO_7_PORT GPIOD +#define GPIO_7_PIN 6 +#define GPIO_7_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN) +#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PD) +#define GPIO_7_IRQ EXTI9_5_IRQn +/* GPIO channel 8 config */ +#define GPIO_8_PORT GPIOD +#define GPIO_8_PIN 7 +#define GPIO_8_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN) +#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PD) +#define GPIO_8_IRQ EXTI9_5_IRQn +/* GPIO channel 9 config */ +#define GPIO_9_PORT GPIOA +#define GPIO_9_PIN 8 +#define GPIO_9_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) +#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA) +#define GPIO_9_IRQ EXTI9_5_IRQn +/* GPIO channel 10 config */ +#define GPIO_10_PORT GPIOA /* LD7 */ +#define GPIO_10_PIN 9 +#define GPIO_10_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN) +#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA) +#define GPIO_10_IRQ EXTI9_5_IRQn +/* GPIO channel 11 config */ +#define GPIO_11_PORT GPIOD +#define GPIO_11_PIN 10 +#define GPIO_11_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN) +#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PD) +#define GPIO_11_IRQ EXTI15_10_IRQn +/** @} */ + +#endif /* __PERIPH_CONF_H */ +/** @} */