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cpu/stm32f0: handle custom pll prediv/mul at cpu level

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Alexandre Abadie 2020-11-10 14:34:44 +01:00
parent 5d77b7d90d
commit 9d13c07e92
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GPG Key ID: 1C919A403CAE1405
1 changed files with 11 additions and 1 deletions
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12
cpu/stm32/include/clk/f0/cfg_clock_default.h
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@ -78,13 +78,23 @@ extern "C" {
#define CLOCK_HSI MHZ(8) #define CLOCK_HSI MHZ(8)
/* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock */ /* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock
On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is hard-wired to 2,
so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */
#ifndef CONFIG_CLOCK_PLL_PREDIV #ifndef CONFIG_CLOCK_PLL_PREDIV
#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_PREDIV (2)
#else
#define CONFIG_CLOCK_PLL_PREDIV (1) #define CONFIG_CLOCK_PLL_PREDIV (1)
#endif #endif
#endif
#ifndef CONFIG_CLOCK_PLL_MUL #ifndef CONFIG_CLOCK_PLL_MUL
#if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
#define CONFIG_CLOCK_PLL_MUL (12)
#else
#define CONFIG_CLOCK_PLL_MUL (6) #define CONFIG_CLOCK_PLL_MUL (6)
#endif #endif
#endif
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI) #define CLOCK_CORECLOCK (CLOCK_HSI)