diff --git a/cpu/stm32/dist/clk_conf/clk_conf.h b/cpu/stm32/dist/clk_conf/clk_conf.h
index 844419dd8a..cdc45b7206 100644
--- a/cpu/stm32/dist/clk_conf/clk_conf.h
+++ b/cpu/stm32/dist/clk_conf/clk_conf.h
@@ -11,8 +11,7 @@
  *
  *
  * @author      Vincent Dupont <vincent@otakeys.com>
- *
- * @}
+ * @{
  */
 
 #ifndef CLK_CONF_H
@@ -26,7 +25,7 @@ extern "C" {
 
 /**
  * @name STM32 families
- * @ {
+ * @{
  */
 enum fam {
     STM32F0,
@@ -115,7 +114,6 @@ enum {
 
     MODEL_MP_MAX,
 };
-
 /** @} */
 
 /**
@@ -631,7 +629,7 @@ static const clk_cfg_t stm32_f_clk_cfg[] = {
     },
 };
 
-    /**
+/**
  * @brief Clock config for supported cpu
  */
 static const clk_cfg_t stm32_mp_clk_cfg[] = {
@@ -658,3 +656,4 @@ static const clk_cfg_t stm32_mp_clk_cfg[] = {
 #endif
 
 #endif /* CLK_CONF_H */
+/** @} */
diff --git a/cpu/stm32/include/clk/cfg_clock_common_lx_wx.h b/cpu/stm32/include/clk/cfg_clock_common_lx_wx.h
index a100cfb3f4..ab6e015aa7 100644
--- a/cpu/stm32/include/clk/cfg_clock_common_lx_wx.h
+++ b/cpu/stm32/include/clk/cfg_clock_common_lx_wx.h
@@ -40,6 +40,7 @@ extern "C" {
 #define CONFIG_USE_CLOCK_PLL            1     /* Use PLL by default */
 #endif
 #endif /* CONFIG_USE_CLOCK_PLL */
+/** @} */
 
 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
     (IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
index 1a98e877de..ed1f54755c 100644
--- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
@@ -75,6 +75,7 @@ extern "C" {
 
 /**
  * @name    Clock bus settings (APB1 and APB2)
+ * @{
  */
 #ifndef CONFIG_CLOCK_APB1_DIV
 #define CONFIG_CLOCK_APB1_DIV           (2)         /* max 50MHz */
diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
index 81fa404500..74b96a87cc 100644
--- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_120.h
@@ -53,6 +53,7 @@ extern "C" {
 
 /**
  * @name    Clock bus settings (APB1 and APB2)
+ * @{
  */
 #ifndef CONFIG_CLOCK_APB1_DIV
 #define CONFIG_CLOCK_APB1_DIV           (4)        /* max 30MHz */
diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
index 775292d98e..f9efcaff36 100644
--- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
@@ -87,6 +87,7 @@ extern "C" {
 
 /**
  * @name    Clock bus settings (APB1 and APB2)
+ * @{
  */
 #ifndef CONFIG_CLOCK_APB1_DIV
 #define CONFIG_CLOCK_APB1_DIV           (4)         /* max 45MHz */
diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
index ca7e3ee590..55e3bf338e 100644
--- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_216.h
@@ -62,6 +62,7 @@ extern "C" {
 
 /**
  * @name    Clock bus settings (APB1 and APB2)
+ * @{
  */
 #ifndef CONFIG_CLOCK_APB1_DIV
 #define CONFIG_CLOCK_APB1_DIV           (4)         /* max 54MHz */
diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
index e3ceeade04..66137a3bcd 100644
--- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_84.h
@@ -62,6 +62,7 @@ extern "C" {
 
 /**
  * @name    Clock bus settings (APB1 and APB2)
+ * @{
  */
 #ifndef CONFIG_CLOCK_APB1_DIV
 #define CONFIG_CLOCK_APB1_DIV           (2)         /* max 42MHz */
diff --git a/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h b/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h
index b8652f3d4c..658d7d9394 100644
--- a/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h
+++ b/cpu/stm32/include/clk/l4l5wx/cfg_clock_default.h
@@ -175,6 +175,7 @@ extern "C" {
 #define CONFIG_CLOCK_APB2_DIV           (2)
 #endif
 #define CLOCK_APB2                      (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV)     /* PCLK1, max: 48/64/80/120MHz */
+/** @} */
 
 #ifdef __cplusplus
 }
diff --git a/cpu/stm32/include/clk/mp1/cfg_clock_default.h b/cpu/stm32/include/clk/mp1/cfg_clock_default.h
index 369ad68cf8..8dd698cb1f 100644
--- a/cpu/stm32/include/clk/mp1/cfg_clock_default.h
+++ b/cpu/stm32/include/clk/mp1/cfg_clock_default.h
@@ -50,6 +50,7 @@
 
 /**
  * @name    MP1 clock bus settings (MCU, APB1, APB2 and APB3)
+ * @{
  */
 #ifndef CONFIG_CLOCK_MCU_DIV
 #define CONFIG_CLOCK_MCU_DIV            (1)         /* max 208MHz */