Merge pull request #14830 from benpicco/cpu/lpc23xx-picolibc

cpu/lpc23xx: enable support for picolibc

cpu/arm7_common/Makefile.dep

@@ -1,4 +1,12 @@
 # use common ARM7 periph code
 USEMODULE += arm7_common_periph
-# use the nano-specs of Newlib when available
-USEMODULE += newlib_nano
+
+ifeq (1,$(PICOLIBC))
+  # Use Picolibc when explicitly selected
+  USEMODULE += picolibc
+else
+  # all cortex MCU's use newlib as libc
+  USEMODULE += newlib
+  # use the nano-specs of Newlib when available
+  USEMODULE += newlib_nano
+endif

cpu/lpc23xx/Makefile.dep

@@ -1,6 +1,5 @@
 USEMODULE += arm7_common
 USEMODULE += bitfield
-USEMODULE += newlib
 USEMODULE += periph
 USEMODULE += pm_layered
 

cpu/lpc23xx/ldscripts/lpc23xx.ld

@@ -70,6 +70,42 @@ SECTIONS
         _efixed = .;            /* End of text section */
     } > rom
 
+    /*
+     * TLS relocations are offsets relative to the address
+     * of the first TLS symbol. That means we just need to
+     * allocate them all together so that the TLS region
+     * is compact when allocated for each thread.
+     */
+
+    /*
+     * TLS initialization data is loaded into ROM so that
+     * each thread can get its values initialized from there
+     * at startup
+     */
+    .tdata :
+    {
+         __tdata_start = .;
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        __tdata_end = .;
+    } > rom
+    __tdata_source = LOADADDR(.tdata);
+    __tdata_size = SIZEOF(.tdata);
+
+    /*
+     * TLS zeroed data is relocated as if it immediately followed
+     * the tdata values. However, the linker 'magically' erases the
+     * memory allocation so that no ROM is consumed by this
+     * section
+     */
+    .tbss :
+    {
+        *(.tbss .tbss.* .gnu.linkonce.tb.*)
+        *(.tcommon)
+        __tbss_end = .;
+    } > rom
+    __tls_size = __tbss_end - __tdata_start;
+    __tbss_size = __tls_size - __tdata_size;
+
     /* .ARM.exidx is sorted, so has to go in its own output section.  */
     PROVIDE_HIDDEN (__exidx_start = .);
     .ARM.exidx :