diff --git a/cpu/stm32/periph/rtc_all.c b/cpu/stm32/periph/rtc_all.c
index 44285e3892..b7f5eb21d4 100644
--- a/cpu/stm32/periph/rtc_all.c
+++ b/cpu/stm32/periph/rtc_all.c
@@ -147,7 +147,7 @@
 #endif
 
 /* figure out sync and async prescaler */
-#if CLOCK_LSE
+#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
 #define PRE_SYNC            (255)
 #define PRE_ASYNC           (127)
 #elif (CLOCK_LSI == 40000)
@@ -168,7 +168,7 @@
 
 /* Use a magic number to determine the initial RTC source. This will be used
    to know if a reset of the RTC is required at initialization. */
-#if CLOCK_LSE
+#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
 #define MAGIC_CLCK_NUMBER       (0x1970)
 #else
 #define MAGIC_CLCK_NUMBER       (0x1971)
@@ -241,7 +241,7 @@ void rtc_init(void)
     /* select input clock and enable the RTC */
     stmclk_dbp_unlock();
     EN_REG &= ~(CLKSEL_MASK);
-#if CLOCK_LSE
+#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
     EN_REG |= (CLKSEL_LSE | EN_BIT);
 #else
     EN_REG |= (CLKSEL_LSI | EN_BIT);
diff --git a/cpu/stm32/periph/rtt_all.c b/cpu/stm32/periph/rtt_all.c
index 2e2cc12da4..375d7bc562 100644
--- a/cpu/stm32/periph/rtt_all.c
+++ b/cpu/stm32/periph/rtt_all.c
@@ -52,7 +52,7 @@
 #if defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
 #define CLOCK_SRC_REG       RCC->DCKCFGR2
 #define CLOCK_SRC_MASK      RCC_DCKCFGR2_LPTIM1SEL
-#if CLOCK_LSE
+#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
 #define CLOCK_SRC_CFG       (RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)
 #else
 #define CLOCK_SRC_CFG       (RCC_DCKCFGR2_LPTIM1SEL_0)
@@ -60,7 +60,7 @@
 #else
 #define CLOCK_SRC_REG       RCC->CCIPR
 #define CLOCK_SRC_MASK      RCC_CCIPR_LPTIM1SEL
-#if CLOCK_LSE
+#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
 #define CLOCK_SRC_CFG       (RCC_CCIPR_LPTIM1SEL_1 | RCC_CCIPR_LPTIM1SEL_0)
 #else
 #define CLOCK_SRC_CFG       (RCC_CCIPR_LPTIM1SEL_0)
diff --git a/cpu/stm32/stmclk/stmclk_common.c b/cpu/stm32/stmclk/stmclk_common.c
index 96193460e8..509e5f91c8 100644
--- a/cpu/stm32/stmclk/stmclk_common.c
+++ b/cpu/stm32/stmclk/stmclk_common.c
@@ -49,8 +49,8 @@
 #define RCC_CSR_LSIRDY          RCC_CSR_LSI1RDY
 #endif
 
-#ifndef CLOCK_LSE
-#define CLOCK_LSE   (0U)
+#ifndef CONFIG_BOARD_HAS_LSE
+#define CONFIG_BOARD_HAS_LSE    0
 #endif
 
 void stmclk_enable_hsi(void)
@@ -66,7 +66,7 @@ void stmclk_disable_hsi(void)
 
 void stmclk_enable_lfclk(void)
 {
-    if (CLOCK_LSE) {
+    if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
         stmclk_dbp_unlock();
         RCC->REG_LSE |= BIT_LSEON;
         while (!(RCC->REG_LSE & BIT_LSERDY)) {}
@@ -80,7 +80,7 @@ void stmclk_enable_lfclk(void)
 
 void stmclk_disable_lfclk(void)
 {
-    if (CLOCK_LSE) {
+    if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
         stmclk_dbp_unlock();
         RCC->REG_LSE &= ~(BIT_LSEON);
         while (!(RCC->REG_LSE & BIT_LSERDY)) {}