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Merge pull request #14166 from aabadie/pr/cpu/stm32g4

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cpu/stm32g4: add support + add nucleo-g474re board
This commit is contained in:
benpicco 2020-06-19 17:05:15 +02:00 committed by GitHub
commit a30d229b12
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GPG Key ID: 4AEE18F83AFDEB23
35 changed files with 18932 additions and 71 deletions
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2
boards/common/nucleo64/include/board.h
View File

@ -54,7 +54,7 @@ extern "C" {
* @{
*/
#define BTN0_PIN GPIO_PIN(PORT_C, 13)
#ifdef CPU_MODEL_STM32L433RC
#if defined(CPU_MODEL_STM32L433RC) || defined(CPU_MODEL_STM32G474RE)
#define BTN0_MODE GPIO_IN_PD
#else
#define BTN0_MODE GPIO_IN_PU

2
boards/common/nucleo64/include/gpio_params.h
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@ -43,7 +43,7 @@ static const saul_gpio_params_t saul_gpio_params[] =
.name = "Button(B1 User)",
.pin = BTN0_PIN,
.mode = BTN0_MODE,
#ifndef CPU_MODEL_STM32L433RC
#if !defined(CPU_MODEL_STM32L433RC) && !defined(CPU_MODEL_STM32G474RE)
.flags = SAUL_GPIO_INVERTED
#endif
},

3
boards/common/stm32/dist/stm32g4.cfg vendored Normal file
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@ -0,0 +1,3 @@
source [find target/stm32g4x.cfg]
reset_config srst_only
$_TARGETNAME configure -rtos auto

2
boards/common/stm32/include/cfg_i2c1_pb8_pb9.h
View File

@ -47,7 +47,7 @@ static const i2c_conf_t i2c_config[] = {
.rcc_mask = RCC_APB1ENR_I2C1EN,
.clk = CLOCK_APB1,
.irqn = I2C1_EV_IRQn,
#elif CPU_FAM_STM32L4 || CPU_FAM_STM32WB
#elif CPU_FAM_STM32L4 || CPU_FAM_STM32WB || CPU_FAM_STM32G4
.rcc_mask = RCC_APB1ENR1_I2C1EN,
.irqn = I2C1_ER_IRQn,
#elif CPU_FAM_STM32F7

4
boards/common/stm32/include/cfg_timer_tim5.h
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@ -33,7 +33,11 @@ static const timer_conf_t timer_config[] = {
{
.dev = TIM5,
.max = 0xffffffff,
#if defined(CPU_FAM_STM32G4)
.rcc_mask = RCC_APB1ENR1_TIM5EN,
#else
.rcc_mask = RCC_APB1ENR_TIM5EN,
#endif
.bus = APB1,
.irqn = TIM5_IRQn
}

81
boards/common/stm32/include/g4/cfg_clock_default.h Normal file
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@ -0,0 +1,81 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32G4 clock
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef G4_CFG_CLOCK_DEFAULT_H
#define G4_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
* @{
*/
#define CLOCK_USE_HSI (0)
#define CLOCK_USE_HSE (0)
#define CLOCK_USE_PLL (1)
#define CLOCK_HSI (16000000U)
#ifndef CLOCK_HSE
#define CLOCK_HSE (24000000U)
#endif
#ifndef CLOCK_LSE
#define CLOCK_LSE (1U)
#endif
#if CLOCK_USE_HSI
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif CLOCK_USE_HSE
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CLOCK_USE_PLL
/* The following parameters configure a 80MHz system clock with HSE as input clock */
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (40)
#define CLOCK_PLL_R (2)
/* Use the following to reach 170MHz
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (85)
#define CLOCK_PLL_R (2)
*/
#if CLOCK_HSE
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_R
#endif
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) /* max 170MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) /* max 170MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) /* max 170MHz */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* G4_CFG_CLOCK_DEFAULT_H */
/** @} */

4
boards/nucleo-g474re/Makefile Normal file
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@ -0,0 +1,4 @@
MODULE = board
DIRS = $(RIOTBOARD)/common/nucleo
include $(RIOTBASE)/Makefile.base

3
boards/nucleo-g474re/Makefile.dep Normal file
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@ -0,0 +1,3 @@
FEATURES_REQUIRED += periph_lpuart
include $(RIOTBOARD)/common/nucleo/Makefile.dep

16
boards/nucleo-g474re/Makefile.features Normal file
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@ -0,0 +1,16 @@
CPU = stm32
CPU_MODEL = stm32g474re
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart periph_lpuart
# Put other features for this board (in alphabetical order)
FEATURES_PROVIDED += riotboot
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/common/nucleo64/Makefile.features

2
boards/nucleo-g474re/Makefile.include Normal file
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@ -0,0 +1,2 @@
# load the common Makefile.include for Nucleo boards
include $(RIOTBOARD)/common/nucleo64/Makefile.include

26
boards/nucleo-g474re/doc.txt Normal file
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@ -0,0 +1,26 @@
/**
@defgroup boards_nucleo-g474re STM32 Nucleo-G474RE
@ingroup boards_common_nucleo64
@brief Support for the STM32 Nucleo-G474RE
## Flashing the device
The ST Nucleo-G474RE board includes an on-board ST-LINK V3 programmer. The
easiest way to program the board is to use OpenOCD. Once you have installed
OpenOCD (look [here](https://github.com/RIOT-OS/RIOT/wiki/OpenOCD) for
installation instructions), you can flash the board simply by typing
```
make BOARD=nucleo-g474re flash
```
and debug via GDB by simply typing
```
make BOARD=nucleo-g474re debug
```
## Supported Toolchains
For using the ST Nucleo-G474RE board we recommend the usage of the
[GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded)
toolchain.
*/

117
boards/nucleo-g474re/include/periph_conf.h Normal file
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@ -0,0 +1,117 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo-g474re
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo-g474re board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "g4/cfg_clock_default.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = LPUART1,
.rcc_mask = RCC_APB1ENR2_LPUART1EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF12,
.tx_af = GPIO_AF12,
.bus = APB12,
.irqn = LPUART1_IRQn,
.type = STM32_LPUART,
.clk_src = 0, /* Use APB clock */
},
{ /* Connected to Arduino D0/D1 */
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_C, 5),
.tx_pin = GPIO_PIN(PORT_C, 4),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn,
.type = STM32_USART,
.clk_src = 0, /* Use APB clock */
},
};
#define UART_0_ISR (isr_lpuart1)
#define UART_1_ISR (isr_usart1)
#define UART_NUMOF ARRAY_SIZE(uart_config)
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 80000000Hz */
7, /* -> 312500Hz */
7, /* -> 312500Hz */
5, /* -> 1250000Hz */
3, /* -> 5000000Hz */
2 /* -> 10000000Hz */
},
{ /* for APB2 @ 80000000Hz */
7, /* -> 312500Hz */
7, /* -> 312500Hz */
5, /* -> 1250000Hz */
3, /* -> 5000000Hz */
2 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */
.miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */
.sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */
.cs_pin = GPIO_UNDEF,
.mosi_af = GPIO_AF5,
.miso_af = GPIO_AF5,
.sclk_af = GPIO_AF5,
.cs_af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2,
},
};
#define SPI_NUMOF ARRAY_SIZE(spi_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

6
cpu/stm32/Makefile.features
View File

@ -9,7 +9,7 @@ FEATURES_PROVIDED += periph_uart_modecfg
FEATURES_PROVIDED += periph_uart_nonblocking
FEATURES_PROVIDED += periph_wdt
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 l0 l1 l4 wb))
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g4 l0 l1 l4 wb))
ifeq (,$(filter nucleo-f031k6,$(BOARD)))
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
@ -27,13 +27,13 @@ endif
# Not all F4 and L0 parts implement a RNG.
CPU_MODELS_WITHOUT_HWRNG = stm32f401% stm32f411% stm32f446% stm32l031%
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 l0 l4 wb))
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l0 l4 wb))
ifeq (,$(filter $(CPU_MODELS_WITHOUT_HWRNG),$(CPU_MODEL)))
FEATURES_PROVIDED += periph_hwrng
endif
endif
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 l1 l4))
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l1 l4))
FEATURES_PROVIDED += cortexm_mpu
endif

21
cpu/stm32/cpu_common.c
View File

@ -51,7 +51,8 @@ uint32_t periph_apb_clk(uint8_t bus)
if (bus == APB1) {
return CLOCK_APB1;
}
#if defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
else if (bus == APB12) {
return CLOCK_APB1;
}
@ -70,7 +71,8 @@ void periph_clk_en(bus_t bus, uint32_t mask)
{
switch (bus) {
case APB1:
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
RCC->APB1ENR1 |= mask;
#else
RCC->APB1ENR |= mask;
@ -79,7 +81,8 @@ void periph_clk_en(bus_t bus, uint32_t mask)
case APB2:
RCC->APB2ENR |= mask;
break;
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
case APB12:
RCC->APB1ENR2 |= mask;
break;
@ -98,7 +101,7 @@ void periph_clk_en(bus_t bus, uint32_t mask)
break;
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
case AHB1:
RCC->AHB1ENR |= mask;
break;
@ -124,7 +127,8 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
{
switch (bus) {
case APB1:
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
RCC->APB1ENR1 &= ~(mask);
#else
RCC->APB1ENR &= ~(mask);
@ -133,7 +137,8 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
case APB2:
RCC->APB2ENR &= ~(mask);
break;
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
case APB12:
RCC->APB1ENR2 &= ~(mask);
break;
@ -152,7 +157,7 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
break;
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
case AHB1:
RCC->AHB1ENR &= ~(mask);
break;
@ -177,7 +182,7 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
}
}
#if defined(CPU_FAM_STM32L4)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4)
void periph_lpclk_en(bus_t bus, uint32_t mask)
{
switch (bus) {

2
cpu/stm32/cpu_init.c
View File

@ -39,7 +39,7 @@
#include "periph/init.h"
#include "board.h"
#if defined (CPU_FAM_STM32L4)
#if defined (CPU_FAM_STM32L4) || defined (CPU_FAM_STM32G4)
#define BIT_APB_PWREN RCC_APB1ENR1_PWREN
#else
#define BIT_APB_PWREN RCC_APB1ENR_PWREN

14
cpu/stm32/include/cpu_conf.h
View File

@ -35,6 +35,8 @@
#include "vendor/stm32f4xx.h"
#elif CPU_FAM_STM32F7
#include "vendor/stm32f7xx.h"
#elif CPU_FAM_STM32G4
#include "vendor/stm32g4xx.h"
#elif CPU_FAM_STM32L0
#include "vendor/stm32l0xx.h"
#elif CPU_FAM_STM32L1
@ -85,7 +87,8 @@ extern "C" {
#define CPU_IRQ_NUMOF (86U)
#elif defined(CPU_LINE_STM32F412Zx) || defined(CPU_LINE_STM32F446xx)
#define CPU_IRQ_NUMOF (97U)
#elif defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
#elif defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx) || \
defined(CPU_LINE_STM32G474xx)
#define CPU_IRQ_NUMOF (102U)
#elif defined(CPU_LINE_STM32F429xx) || defined(CPU_LINE_STM32F437xx)
#define CPU_IRQ_NUMOF (91U)
@ -128,7 +131,8 @@ extern "C" {
#define FLASHPAGE_SIZE (4096U)
#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
|| defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4)
|| defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
|| defined(CPU_FAM_STM32G4)
#define FLASHPAGE_SIZE (2048U)
#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
|| defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
@ -145,7 +149,8 @@ extern "C" {
/* The minimum block size which can be written depends on the family.
* However, the erase block is always FLASHPAGE_SIZE.
*/
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#define FLASHPAGE_RAW_BLOCKSIZE (8U)
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define FLASHPAGE_RAW_BLOCKSIZE (4U)
@ -153,7 +158,8 @@ extern "C" {
#define FLASHPAGE_RAW_BLOCKSIZE (2U)
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#define FLASHPAGE_RAW_ALIGNMENT (8U)
#else
/* Writing should be always 4 bytes aligned */

8
cpu/stm32/include/cpu_conf_stm32_common.h
View File

@ -30,7 +30,7 @@ extern "C" {
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
/**
* @brief Timing register settings
@ -39,7 +39,8 @@ extern "C" {
*/
static const i2c_timing_param_t timing_params[] = {
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
[ I2C_SPEED_NORMAL ] = {
.presc = 0xB,
.scll = 0x13, /* t_SCLL = 5.0us */
@ -109,7 +110,8 @@ static const i2c_timing_param_t timing_params[] = {
};
#endif /* CPU_FAM_STM32F0 || CPU_FAM_STM32F3 || CPU_FAM_STM32F7 ||
CPU_FAM_STM32L0 || CPU_FAM_STM32L4 || CPU_FAM_STM32WB */
CPU_FAM_STM32L0 || CPU_FAM_STM32L4 || CPU_FAM_STM32WB ||
CPU_FAM_STM32G4*/
#ifdef __cplusplus
}

42
cpu/stm32/include/periph/g4/periph_cpu.h Normal file
View File

@ -0,0 +1,42 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief STM3G4 CPU specific definitions for internal peripheral handling
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
*/
#ifndef PERIPH_G4_PERIPH_CPU_H
#define PERIPH_G4_PERIPH_CPU_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef DOXYGEN
/**
* @brief Starting address of the ROM bootloader
* see application note AN2606
*/
#define STM32_BOOTLOADER_ADDR (0x1FFF0000)
#endif /* ndef DOXYGEN */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_G4_PERIPH_CPU_H */
/** @} */

25
cpu/stm32/include/periph_cpu.h
View File

@ -35,6 +35,8 @@
#include "periph/f4/periph_cpu.h"
#elif defined(CPU_FAM_STM32F7)
#include "periph/f7/periph_cpu.h"
#elif defined(CPU_FAM_STM32G4)
#include "periph/g4/periph_cpu.h"
#elif defined(CPU_FAM_STM32L0)
#include "periph/l0/periph_cpu.h"
#elif defined(CPU_FAM_STM32L1)
@ -59,7 +61,7 @@ extern "C" {
#define CLOCK_LSI (37000U)
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
#define CLOCK_LSI (32000U)
#else
#error "error: LSI clock speed not defined for your target CPU"
@ -164,7 +166,8 @@ extern "C" {
typedef enum {
APB1, /**< APB1 bus */
APB2, /**< APB2 bus */
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
APB12, /**< AHB1 bus, second register */
#endif
#if defined(CPU_FAM_STM32L0)
@ -175,7 +178,7 @@ typedef enum {
AHB, /**< AHB bus */
#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
AHB1, /**< AHB1 bus */
AHB2, /**< AHB2 bus */
AHB3, /**< AHB3 bus */
@ -220,17 +223,19 @@ enum {
#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1) || \
defined(CPU_FAM_STM32L4)
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4)
PORT_G = 6, /**< port G */
#endif
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
PORT_H = 7, /**< port H */
#endif
#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4)
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32G4)
PORT_I = 8, /**< port I */
#endif
#if defined(CPU_FAM_STM32F7)
@ -629,7 +634,7 @@ typedef struct {
#endif
#endif
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
uart_type_t type; /**< hardware module type (USART or LPUART) */
uint32_t clk_src; /**< clock source used for UART */
#endif
@ -679,7 +684,8 @@ typedef enum {
I2C_SPEED_FAST, /**< fast mode: ~400kbit/s */
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
I2C_SPEED_FAST_PLUS, /**< fast plus mode: ~1Mbit/s */
#endif
} i2c_speed_t;
@ -712,7 +718,8 @@ typedef struct {
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
/**
* @brief Structure for I2C timing register settings
*

17910
cpu/stm32/include/vendor/stm32g474xx.h vendored Normal file
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File diff suppressed because it is too large Load Diff

199
cpu/stm32/include/vendor/stm32g4xx.h vendored Normal file
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@ -0,0 +1,199 @@
/**
******************************************************************************
* @file stm32g4xx.h
* @author MCD Application Team
* @brief CMSIS STM32G4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32G4xx device used in the target application
* - To use or not the peripheral<EFBFBD>s drivers in application code(i.e.
* code will be based on direct access to peripheral<EFBFBD>s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g4xx
* @{
*/
#ifndef __STM32G4xx_H
#define __STM32G4xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32G4)
#define STM32G4
#endif /* STM32G4 */
/* Uncomment the line below according to the target STM32G4 device used in your
application
*/
#if !defined (STM32G431xx) && !defined (STM32G441xx) && \
!defined (STM32G471xx) && !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && !defined (STM32GBK1CB)
/* #define STM32G431xx */ /*!< STM32G431xx Devices */
/* #define STM32G441xx */ /*!< STM32G441xx Devices */
/* #define STM32G471xx */ /*!< STM32G471xx Devices */
/* #define STM32G473xx */ /*!< STM32G473xx Devices */
/* #define STM32G483xx */ /*!< STM32G483xx Devices */
/* #define STM32G474xx */ /*!< STM32G474xx Devices */
/* #define STM32G484xx */ /*!< STM32G484xx Devices */
/* #define STM32GBK1CB */ /*!< STM32GBK1CB Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.1.1
*/
#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32G4_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
|(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
|(__STM32G4_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32G4_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32G431xx)
#include "stm32g431xx.h"
#elif defined(STM32G441xx)
#include "stm32g441xx.h"
#elif defined(STM32G471xx)
#include "stm32g471xx.h"
#elif defined(STM32G473xx)
#include "stm32g473xx.h"
#elif defined(STM32G483xx)
#include "stm32g483xx.h"
#elif defined(STM32G474xx)
#include "stm32g474xx.h"
#elif defined(STM32G484xx)
#include "stm32g484xx.h"
#elif defined(STM32GBK1CB)
#include "stm32gbk1cb.h"
#else
#error "Please select first the target STM32G4xx device used in your application (in stm32g4xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32g4xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G4xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
cpu/stm32/periph/Makefile
View File

@ -2,7 +2,7 @@ MODULE = periph
# Select the specific implementation for `periph_i2c`
ifneq (,$(filter periph_i2c,$(USEMODULE)))
ifneq (,$(filter $(CPU_FAM),f0 f3 f7 l0 l4 wb))
ifneq (,$(filter $(CPU_FAM),f0 f3 f7 g4 l0 l4 wb))
SRC += i2c_1.c
else # f1/f2/f4/l1
SRC += i2c_2.c

3
cpu/stm32/periph/flash_common.c
View File

@ -32,7 +32,8 @@
#define CNTRL_REG_LOCK (FLASH_PECR_PELOCK)
#define KEY_REG (FLASH->PEKEYR)
#else
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#endif

28
cpu/stm32/periph/flashpage.c
View File

@ -40,7 +40,8 @@
#define FLASH_CR_PER (FLASH_PECR_ERASE | FLASH_PECR_PROG)
#define FLASHPAGE_DIV (4U) /* write 4 bytes in one go */
#else
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#define FLASHPAGE_DIV (8U)
#else
#define FLASHPAGE_DIV (2U)
@ -53,6 +54,12 @@ extern void _lock(void);
extern void _unlock(void);
extern void _wait_for_pending_operations(void);
#if defined(CPU_FAM_STM32G4)
#define MAX_PAGES_PER_BANK (128)
#else /* CPU_FAM_STM32L4 */
#define MAX_PAGES_PER_BANK (256)
#endif
static void _unlock_flash(void)
{
_unlock();
@ -72,7 +79,8 @@ static void _unlock_flash(void)
static void _erase_page(void *page_addr)
{
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
uint32_t *dst = page_addr;
#else
uint16_t *dst = page_addr;
@ -97,14 +105,15 @@ static void _erase_page(void *page_addr)
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
DEBUG("[flashpage] erase: trigger the page erase\n");
*dst = (uint32_t)0;
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
DEBUG("[flashpage] erase: setting the page address\n");
uint8_t pn;
#if (FLASHPAGE_NUMOF <= 256) || defined(CPU_FAM_STM32WB)
#if (FLASHPAGE_NUMOF <= MAX_PAGES_PER_BANK) || defined(CPU_FAM_STM32WB)
pn = (uint8_t)flashpage_page(dst);
#else
uint16_t page = flashpage_page(dst);
if (page > 255) {
if (page > MAX_PAGES_PER_BANK - 1) {
CNTRL_REG |= FLASH_CR_BKER;
}
else {
@ -158,7 +167,8 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
uint32_t *dst = target_addr;
const uint32_t *data_addr = data;
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
uint64_t *dst = target_addr;
const uint64_t *data_addr = data;
#else
@ -182,7 +192,7 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
DEBUG("[flashpage_raw] write: now writing the data\n");
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
/* set PG bit and program page to flash */
CNTRL_REG |= FLASH_CR_PG;
#endif
@ -196,7 +206,7 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
/* clear program bit again */
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
CNTRL_REG &= ~(FLASH_CR_PG);
#endif
DEBUG("[flashpage_raw] write: done writing data\n");
@ -225,7 +235,7 @@ void flashpage_write(int page, const void *data)
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
/* STM32L0/L1 only supports word sizes */
uint32_t *page_addr = flashpage_addr(page);
#elif defined(CPU_FAM_STM32L4)
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4)
uint64_t *page_addr = flashpage_addr(page);
#else
/* Default is to support half-word sizes */

9
cpu/stm32/periph/gpio_all.c
View File

@ -43,7 +43,8 @@
static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
#endif /* MODULE_PERIPH_GPIO_IRQ */
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#define EXTI_REG_RTSR (EXTI->RTSR1)
#define EXTI_REG_FTSR (EXTI->FTSR1)
#define EXTI_REG_PR (EXTI->PR1)
@ -92,7 +93,8 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined (CPU_FAM_STM32G4)
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#ifdef PWR_CR2_IOSV
if (port == GPIOG) {
@ -141,7 +143,8 @@ void gpio_init_analog(gpio_t pin)
periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L0)
periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#elif defined (CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined (CPU_FAM_STM32G4)
periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
#else
periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));

12
cpu/stm32/periph/pm.c
View File

@ -46,7 +46,7 @@
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
/* Enable ultra low-power and clear wakeup flags */
#define PM_STOP_CONFIG (PWR_CR_LPSDSR | PWR_CR_ULP | PWR_CR_CWUF)
#elif defined(CPU_FAM_STM32L4)
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4)
#define PM_STOP_CONFIG (PWR_CR1_LPMS_STOP1)
#elif defined(CPU_FAM_STM32WB)
#define PM_STOP_CONFIG (PWR_CR1_LPMS_0)
@ -66,7 +66,7 @@
*/
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF | PWR_CR_ULP)
#elif defined(CPU_FAM_STM32L4)
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4)
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_STANDBY)
#elif defined(CPU_FAM_STM32WB)
#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
@ -77,7 +77,8 @@
#endif
#endif
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#define PWR_CR_REG PWR->CR1
#define PWR_WUP_REG PWR->CR3
/* Allow overridable SRAM2 retention mode using CFLAGS */
@ -102,14 +103,15 @@ void pm_set(unsigned mode)
case STM32_PM_STANDBY:
PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
PWR_CR_REG |= PM_STANDBY_CONFIG;
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#if STM32L4_SRAM2_RETENTION
PWR->CR3 |= PWR_CR3_RRS;
#else
PWR->CR3 &= ~PWR_CR3_RRS;
#endif
#endif
#if defined(CPU_FAM_STM32L4)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4)
/* Clear flags */
PWR->SCR |= PWR_SCR_CSBF;
#endif

38
cpu/stm32/periph/rtc_all.c
View File

@ -43,7 +43,8 @@
#endif
/* map some EXTI register names */
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
defined(CPU_FAM_STM32G4)
#define EXTI_REG_RTSR (EXTI->RTSR1)
#define EXTI_REG_FTSR (EXTI->FTSR1)
#define EXTI_REG_PR (EXTI->PR1)
@ -55,6 +56,19 @@
#define EXTI_REG_IMR (EXTI->IMR)
#endif
/* map some RTC register names and bitfield */
#if defined(CPU_FAM_STM32G4)
#define RTC_REG_ISR RTC->ICSR
#define RTC_ISR_RSF RTC_ICSR_RSF
#define RTC_ISR_INIT RTC_ICSR_INIT
#define RTC_ISR_INITF RTC_ICSR_INITF
#define RTC_ISR_ALRAWF RTC_ICSR_ALRAWF
#define RTC_ISR_ALRAF RTC_SR_ALRAF
#else
#define RTC_REG_ISR RTC->ISR
#endif
/* interrupt line name mapping */
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0)
#define IRQN (RTC_IRQn)
@ -70,7 +84,7 @@
#define EXTI_FTSR_BIT (EXTI_FTSR1_FT18)
#define EXTI_RTSR_BIT (EXTI_RTSR1_RT18)
#define EXTI_PR_BIT (EXTI_PR1_PIF18)
#elif defined(CPU_FAM_STM32WB)
#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
#define EXTI_IMR_BIT (EXTI_IMR1_IM17)
#define EXTI_FTSR_BIT (EXTI_FTSR1_FT17)
#define EXTI_RTSR_BIT (EXTI_RTSR1_RT17)
@ -192,15 +206,15 @@ static inline void rtc_unlock(void)
RTC->WPR = WPK1;
RTC->WPR = WPK2;
/* enter RTC init mode */
RTC->ISR |= RTC_ISR_INIT;
while (!(RTC->ISR & RTC_ISR_INITF)) {}
RTC_REG_ISR |= RTC_ISR_INIT;
while (!(RTC_REG_ISR & RTC_ISR_INITF)) {}
}
static inline void rtc_lock(void)
{
/* exit RTC init mode */
RTC->ISR &= ~RTC_ISR_INIT;
while (RTC->ISR & RTC_ISR_INITF) {}
RTC_REG_ISR &= ~RTC_ISR_INIT;
while (RTC_REG_ISR & RTC_ISR_INITF) {}
/* lock RTC device */
RTC->WPR = 0xff;
/* disable backup clock domain */
@ -237,7 +251,7 @@ void rtc_init(void)
rtc_unlock();
/* reset configuration */
RTC->CR = 0;
RTC->ISR = RTC_ISR_INIT;
RTC_REG_ISR = RTC_ISR_INIT;
/* configure prescaler (RTC PRER) */
RTC->PRER = (PRE_SYNC | (PRE_ASYNC << 16));
rtc_lock();
@ -266,7 +280,7 @@ int rtc_set_time(struct tm *time)
val2bcd(time->tm_min, RTC_TR_MNU_Pos, TR_M_MASK) |
val2bcd(time->tm_sec, RTC_TR_SU_Pos, TR_S_MASK));
rtc_lock();
while (!(RTC->ISR & RTC_ISR_RSF)) {}
while (!(RTC_REG_ISR & RTC_ISR_RSF)) {}
return 0;
}
@ -307,7 +321,7 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
val2bcd(time->tm_sec, RTC_ALRMAR_SU_Pos, ALRM_S_MASK));
/* Enable Alarm A */
RTC->ISR &= ~(RTC_ISR_ALRAF);
RTC_REG_ISR &= ~(RTC_ISR_ALRAF);
RTC->CR |= (RTC_CR_ALRAE | RTC_CR_ALRAIE);
rtc_lock();
@ -333,7 +347,7 @@ int rtc_get_alarm(struct tm *time)
void rtc_clear_alarm(void)
{
RTC->CR &= ~(RTC_CR_ALRAE | RTC_CR_ALRAIE);
while (!(RTC->ISR & RTC_ISR_ALRAWF)) {}
while (!(RTC_REG_ISR & RTC_ISR_ALRAWF)) {}
isr_ctx.cb = NULL;
isr_ctx.arg = NULL;
@ -355,11 +369,11 @@ void rtc_poweroff(void)
void ISR_NAME(void)
{
if (RTC->ISR & RTC_ISR_ALRAF) {
if (RTC_REG_ISR & RTC_ISR_ALRAF) {
if (isr_ctx.cb != NULL) {
isr_ctx.cb(isr_ctx.arg);
}
RTC->ISR &= ~RTC_ISR_ALRAF;
RTC_REG_ISR &= ~RTC_ISR_ALRAF;
}
EXTI_REG_PR = EXTI_PR_BIT; /* only clear the associated bit */
cortexm_isr_end();

7
cpu/stm32/periph/rtt_all.c
View File

@ -70,6 +70,9 @@
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
#define IMR_REG IMR2
#define EXTI_IMR_BIT EXTI_IMR2_IM32
#elif defined(CPU_FAM_STM32G4)
#define IMR_REG IMR2
#define EXTI_IMR_BIT EXTI_IMR2_IM37
#elif defined(CPU_FAM_STM32L0)
#define IMR_REG IMR
#define EXTI_IMR_BIT EXTI_IMR_IM29
@ -112,7 +115,7 @@ void rtt_init(void)
* Needs to be configured to trigger on rising edges. */
EXTI->IMR_REG |= EXTI_IMR_BIT;
#if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
!defined(CPU_FAM_STM32WB)
!defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32G4)
EXTI->FTSR_REG &= ~(EXTI_FTSR_BIT);
EXTI->RTSR_REG |= EXTI_RTSR_BIT;
EXTI->PR_REG = EXTI_PR_BIT;
@ -205,7 +208,7 @@ void isr_lptim1(void)
}
LPTIM1->ICR = (LPTIM_ICR_ARRMCF | LPTIM_ICR_CMPMCF);
#if !defined(CPU_FAM_STM32L4) && !defined(CPU_FAM_STM32L0) && \
!defined(CPU_FAM_STM32WB)
!defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32G4)
EXTI->PR_REG = EXTI_PR_BIT; /* only clear the associated bit */
#endif

9
cpu/stm32/periph/uart.c
View File

@ -36,7 +36,8 @@
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32F7)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32G4)
#define ISR_REG ISR
#define ISR_TXE USART_ISR_TXE
#define ISR_RXNE USART_ISR_RXNE
@ -83,7 +84,7 @@ static inline USART_TypeDef *dev(uart_t uart)
static inline void uart_init_usart(uart_t uart, uint32_t baudrate);
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
#ifdef MODULE_PERIPH_LPUART
static inline void uart_init_lpuart(uart_t uart, uint32_t baudrate);
#endif
@ -181,7 +182,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
dev(uart)->CR3 = 0;
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
switch (uart_config[uart].type) {
case STM32_USART:
uart_init_usart(uart, baudrate);
@ -287,7 +288,7 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate)
}
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
#ifdef MODULE_PERIPH_LPUART
static inline void uart_init_lpuart(uart_t uart, uint32_t baudrate)
{

4
cpu/stm32/stm32_info.mk
View File

@ -1,6 +1,6 @@
# Extract STM32 infos from CPU_MODEL
CPU_MODEL_UPPERCASE = $(call uppercase,$(CPU_MODEL))
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W)([0-7]|B)([A-Z0-9])([0-9])(.)(.)(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
STM32_INFO := $(shell echo $(CPU_MODEL_UPPERCASE) | sed -E -e 's/^STM32(F|L|W|G)([0-7]|B)([A-Z0-9])([0-9])(.)(.)(_A)?/\1 \2 \2\3\4 \3 \4 \5 \6 \7/')
STM32_TYPE = $(word 1, $(STM32_INFO))
STM32_FAMILY = $(word 2, $(STM32_INFO))
STM32_MODEL = $(word 3, $(STM32_INFO))
@ -18,7 +18,7 @@ else ifneq (,$(filter $(CPU_FAM),f1 f2 l1))
CPU_CORE = cortex-m3
else ifneq (,$(filter $(CPU_FAM),f3 f4 l4))
CPU_CORE = cortex-m4f
else ifeq (wb,$(CPU_FAM))
else ifneq (,$(filter $(CPU_FAM),g4 wb))
CPU_CORE = cortex-m4
else ifeq (f7,$(CPU_FAM))
CPU_CORE = cortex-m7

7
cpu/stm32/stm32_mem_lengths.mk
View File

@ -250,6 +250,13 @@ else ifeq ($(STM32_TYPE), L)
RAM_LEN = 640K
endif
endif
else ifeq ($(STM32_TYPE), G)
ifeq ($(STM32_FAMILY), 4)
ifeq ($(STM32_MODEL), 474)
RAM_LEN = 96K
CCMRAM_LEN = 32K
endif
endif
else ifeq ($(STM32_TYPE), W)
ifeq ($(STM32_FAMILY), B)
ifeq ($(STM32_MODEL), B55)

2
cpu/stm32/stmclk/Makefile
View File

@ -8,6 +8,8 @@ else ifneq (,$(filter $(CPU_FAM),l0 l1))
SRC += stmclk_l0l1.c
else ifneq (,$(filter $(CPU_FAM),l4 wb))
SRC += stmclk_l4wb.c
else ifneq (,$(filter $(CPU_FAM),g4))
SRC += stmclk_g4.c
endif
include $(RIOTBASE)/Makefile.base

2
cpu/stm32/stmclk/stmclk_common.c
View File

@ -24,7 +24,7 @@
#include "periph_conf.h"
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
defined(CPU_FAM_STM32WB)
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4)
#define REG_PWR_CR CR1
#define BIT_CR_DBP PWR_CR1_DBP
#else

134
cpu/stm32/stmclk/stmclk_g4.c Normal file
View File

@ -0,0 +1,134 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Implementation of STM32 clock configuration for the G4 family
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @}
*/
#include "cpu.h"
#include "stmclk.h"
#include "periph_conf.h"
#if CLOCK_USE_HSE && CLOCK_HSE == 0
#error "HSE is selected as input clock source but CLOCK_HSE is not set"
#endif
#if CLOCK_USE_PLL
#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 16)
#error "PLL configuration: PLL M value is out of range"
#endif
#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 127)
#error "PLL configuration: PLL N value is out of range"
#endif
#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
#if (CLOCK_PLL_R < 1 || CLOCK_PLL_R > 8)
#error "PLL configuration: PLL R value is out of range"
#endif
#define PLL_R (((CLOCK_PLL_R >> 1) - 1) << RCC_PLLCFGR_PLLR_Pos)
#if CLOCK_HSE
#define PLL_IN CLOCK_HSE
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
#else
#define PLL_IN CLOCK_HSI
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
#endif
#endif /* CLOCK_USE_PLL */
/** Determine the required flash wait states from the core clock frequency */
#if CLOCK_AHB >= 136
#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_4WS) /* 4 ws */
#elif CLOCK_AHB >= 102
#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_3WS) /* 3 ws */
#elif CLOCK_AHB >= 68
#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_2WS) /* 2 ws */
#elif CLOCK_AHB >= 34
#define FLASH_WAITSTATES (FLASH_ACR_LATENCY_1WS) /* 1 ws */
#else
#define FLASH_WAITSTATES (0) /* 0 ws */
#endif
void stmclk_init_sysclk(void)
{
/* disable any interrupts. Global interrupts could be enabled if this is
* called from some kind of bootloader... */
unsigned is = irq_disable();
/* enable HSI clock for the duration of initialization */
stmclk_enable_hsi();
RCC->CIER = 0;
/* use HSI as system clock while we do any further configuration and
* configure the AHB and APB clock dividers as configured by the board */
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
/* we enable I+D caches, pre-fetch, and we set the actual number of
* needed flash wait states */
FLASH->ACR |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN |
FLASH_WAITSTATES);
/* disable all active clocks except HSI -> resets the clk configuration */
RCC->CR = RCC_CR_HSION;
#if CLOCK_LSE
stmclk_enable_lfclk();
#endif
#if CLOCK_USE_HSE
/* if configured, we need to enable the HSE clock now */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {}
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
#elif CLOCK_USE_PLL
#if CLOCK_HSE
/* if configured, we need to enable the HSE clock now */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {}
#endif
/* now we can safely configure and start the PLL */
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
/* now that the PLL is running, we use it as system clock */
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
#endif
stmclk_disable_hsi();
irq_restore(is);
#ifdef MODULE_PERIPH_HWRNG
/* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {}
#endif
#ifdef MODULE_PERIPH_RTT
/* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing
the clock, this is particularly useful after waking up from deep sleep */
#if CLOCK_LSE
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1;
#else
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0;
#endif /* CLOCK_LSE */
#endif /* MODULE_PERIPH_RTT */
}

257
cpu/stm32/vectors/vectors_g4.c Normal file
View File

@ -0,0 +1,257 @@
/*
* Copyright (C) 2020
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_stm32
* @{
*
* @file
* @brief Interrupt vector definitions for STM32G4
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
#include "vectors_cortexm.h"
/* define a local dummy handler as it needs to be in the same compilation unit
* as the alias definition */
void dummy_handler(void) {
dummy_handler_default();
}
/* STM32L4 specific interrupt vectors */
WEAK_DEFAULT void isr_adc1(void);
WEAK_DEFAULT void isr_adc1_2(void);
WEAK_DEFAULT void isr_adc3(void);
WEAK_DEFAULT void isr_adc4(void);
WEAK_DEFAULT void isr_adc5(void);
WEAK_DEFAULT void isr_can1_rx0(void);
WEAK_DEFAULT void isr_can1_rx1(void);
WEAK_DEFAULT void isr_can1_sce(void);
WEAK_DEFAULT void isr_can1_tx(void);
WEAK_DEFAULT void isr_can2_rx0(void);
WEAK_DEFAULT void isr_can2_rx1(void);
WEAK_DEFAULT void isr_can2_sce(void);
WEAK_DEFAULT void isr_can2_tx(void);
WEAK_DEFAULT void isr_comp1_2_3(void);
WEAK_DEFAULT void isr_comp4_5_6(void);
WEAK_DEFAULT void isr_comp7(void);
WEAK_DEFAULT void isr_cordic(void);
WEAK_DEFAULT void isr_crs(void);
WEAK_DEFAULT void isr_dcmi(void);
WEAK_DEFAULT void isr_dfsdm1_flt0(void);
WEAK_DEFAULT void isr_dfsdm1_flt1(void);
WEAK_DEFAULT void isr_dfsdm1_flt2(void);
WEAK_DEFAULT void isr_dfsdm1_flt3(void);
WEAK_DEFAULT void isr_dmamux(void);
WEAK_DEFAULT void isr_dma1_channel1(void);
WEAK_DEFAULT void isr_dma1_channel2(void);
WEAK_DEFAULT void isr_dma1_channel3(void);
WEAK_DEFAULT void isr_dma1_channel4(void);
WEAK_DEFAULT void isr_dma1_channel5(void);
WEAK_DEFAULT void isr_dma1_channel6(void);
WEAK_DEFAULT void isr_dma1_channel7(void);
WEAK_DEFAULT void isr_dma1_channel8(void);
WEAK_DEFAULT void isr_dma2_channel1(void);
WEAK_DEFAULT void isr_dma2_channel2(void);
WEAK_DEFAULT void isr_dma2_channel3(void);
WEAK_DEFAULT void isr_dma2_channel4(void);
WEAK_DEFAULT void isr_dma2_channel5(void);
WEAK_DEFAULT void isr_dma2_channel6(void);
WEAK_DEFAULT void isr_dma2_channel7(void);
WEAK_DEFAULT void isr_dma2_channel8(void);
WEAK_DEFAULT void isr_dma2d(void);
WEAK_DEFAULT void isr_dmamux1_ovr(void);
WEAK_DEFAULT void isr_exti(void);
WEAK_DEFAULT void isr_fdcan1_it0(void);
WEAK_DEFAULT void isr_fdcan1_it1(void);
WEAK_DEFAULT void isr_fdcan2_it0(void);
WEAK_DEFAULT void isr_fdcan2_it1(void);
WEAK_DEFAULT void isr_fdcan3_it0(void);
WEAK_DEFAULT void isr_fdcan3_it1(void);
WEAK_DEFAULT void isr_flash(void);
WEAK_DEFAULT void isr_fmc(void);
WEAK_DEFAULT void isr_fmac(void);
WEAK_DEFAULT void isr_fpu(void);
WEAK_DEFAULT void isr_hrtim1_flt(void);
WEAK_DEFAULT void isr_hrtim1_master(void);
WEAK_DEFAULT void isr_hrtim1_tima(void);
WEAK_DEFAULT void isr_hrtim1_timb(void);
WEAK_DEFAULT void isr_hrtim1_timc(void);
WEAK_DEFAULT void isr_hrtim1_timd(void);
WEAK_DEFAULT void isr_hrtim1_time(void);
WEAK_DEFAULT void isr_hrtim1_timf(void);
WEAK_DEFAULT void isr_i2c1_er(void);
WEAK_DEFAULT void isr_i2c1_ev(void);
WEAK_DEFAULT void isr_i2c2_er(void);
WEAK_DEFAULT void isr_i2c2_ev(void);
WEAK_DEFAULT void isr_i2c3_er(void);
WEAK_DEFAULT void isr_i2c3_ev(void);
WEAK_DEFAULT void isr_i2c4_ev(void);
WEAK_DEFAULT void isr_i2c4_er(void);
WEAK_DEFAULT void isr_lcd(void);
WEAK_DEFAULT void isr_lptim1(void);
WEAK_DEFAULT void isr_lptim2(void);
WEAK_DEFAULT void isr_lpuart1(void);
WEAK_DEFAULT void isr_octospi1(void);
WEAK_DEFAULT void isr_octospi2(void);
WEAK_DEFAULT void isr_otg_fs(void);
WEAK_DEFAULT void isr_pvd_pvm(void);
WEAK_DEFAULT void isr_quadspi(void);
WEAK_DEFAULT void isr_rcc(void);
WEAK_DEFAULT void isr_rng(void);
WEAK_DEFAULT void isr_rtc_alarm(void);
WEAK_DEFAULT void isr_rtc_tamp_lsecss(void);
WEAK_DEFAULT void isr_rtc_wkup(void);
WEAK_DEFAULT void isr_sai1(void);
WEAK_DEFAULT void isr_sai2(void);
WEAK_DEFAULT void isr_sdmmc1(void);
WEAK_DEFAULT void isr_spi1(void);
WEAK_DEFAULT void isr_spi2(void);
WEAK_DEFAULT void isr_spi3(void);
WEAK_DEFAULT void isr_spi4(void);
WEAK_DEFAULT void isr_swpmi1(void);
WEAK_DEFAULT void isr_tim1_brk_tim15(void);
WEAK_DEFAULT void isr_tim1_cc(void);
WEAK_DEFAULT void isr_tim1_trg_com(void);
WEAK_DEFAULT void isr_tim1_trg_com_tim17(void);
WEAK_DEFAULT void isr_tim1_up_tim16(void);
WEAK_DEFAULT void isr_tim2(void);
WEAK_DEFAULT void isr_tim3(void);
WEAK_DEFAULT void isr_tim4(void);
WEAK_DEFAULT void isr_tim5(void);
WEAK_DEFAULT void isr_tim6_dac(void);
WEAK_DEFAULT void isr_tim7_dac(void);
WEAK_DEFAULT void isr_tim8_brk(void);
WEAK_DEFAULT void isr_tim8_cc(void);
WEAK_DEFAULT void isr_tim8_trg_com(void);
WEAK_DEFAULT void isr_tim8_up(void);
WEAK_DEFAULT void isr_tim20_brk(void);
WEAK_DEFAULT void isr_tim20_up(void);
WEAK_DEFAULT void isr_tim20_trg_com(void);
WEAK_DEFAULT void isr_tim20_cc(void);
WEAK_DEFAULT void isr_tsc(void);
WEAK_DEFAULT void isr_uart4(void);
WEAK_DEFAULT void isr_uart5(void);
WEAK_DEFAULT void isr_ucpd1(void);
WEAK_DEFAULT void isr_usart1(void);
WEAK_DEFAULT void isr_usart2(void);
WEAK_DEFAULT void isr_usart3(void);
WEAK_DEFAULT void isr_usb(void);
WEAK_DEFAULT void isr_usb_hp(void);
WEAK_DEFAULT void isr_usb_lp(void);
WEAK_DEFAULT void isr_usbwakeup(void);
WEAK_DEFAULT void isr_wwdg(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
/* shared vectors for all family members */
[WWDG_IRQn ] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */
[PVD_PVM_IRQn ] = isr_pvd_pvm, /* [ 1] PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
[RTC_TAMP_LSECSS_IRQn ] = isr_rtc_tamp_lsecss, /* [ 2] RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
[RTC_WKUP_IRQn ] = isr_rtc_wkup, /* [ 3] RTC Wakeup interrupt through the EXTI line */
[FLASH_IRQn ] = isr_flash, /* [ 4] FLASH global Interrupt */
[RCC_IRQn ] = isr_rcc, /* [ 5] RCC global Interrupt */
[EXTI0_IRQn ] = isr_exti, /* [ 6] EXTI Line0 Interrupt */
[EXTI1_IRQn ] = isr_exti, /* [ 7] EXTI Line1 Interrupt */
[EXTI2_IRQn ] = isr_exti, /* [ 8] EXTI Line2 Interrupt */
[EXTI3_IRQn ] = isr_exti, /* [ 9] EXTI Line3 Interrupt */
[EXTI4_IRQn ] = isr_exti, /* [10] EXTI Line4 Interrupt */
[DMA1_Channel1_IRQn ] = isr_dma1_channel1, /* [11] DMA1 Channel 1 global Interrupt */
[DMA1_Channel2_IRQn ] = isr_dma1_channel2, /* [12] DMA1 Channel 2 global Interrupt */
[DMA1_Channel3_IRQn ] = isr_dma1_channel3, /* [13] DMA1 Channel 3 global Interrupt */
[DMA1_Channel4_IRQn ] = isr_dma1_channel4, /* [14] DMA1 Channel 4 global Interrupt */
[DMA1_Channel5_IRQn ] = isr_dma1_channel5, /* [15] DMA1 Channel 5 global Interrupt */
[DMA1_Channel6_IRQn ] = isr_dma1_channel6, /* [16] DMA1 Channel 6 global Interrupt */
[DMA1_Channel7_IRQn ] = isr_dma1_channel7, /* [17] DMA1 Channel 7 global Interrupt */
[ADC1_2_IRQn ] = isr_adc1_2, /* [18] ADC1, ADC2 SAR global Interrupts */
[USB_HP_IRQn ] = isr_usb_hp, /* [19] USB HP Interrupt */
[USB_LP_IRQn ] = isr_usb_lp, /* [20] USB LP Interrupt */
[FDCAN1_IT0_IRQn ] = isr_fdcan1_it0, /* [21] FDCAN1 IT0 Interrupt */
[FDCAN1_IT1_IRQn ] = isr_fdcan1_it1, /* [22] FDCAN1 IT1 Interrupt */
[EXTI9_5_IRQn ] = isr_exti, /* [23] External Line[9:5] Interrupts */
[TIM1_BRK_TIM15_IRQn ] = isr_tim1_brk_tim15, /* [24] TIM1 Break interrupt and TIM15 global interrupt */
[TIM1_UP_TIM16_IRQn ] = isr_tim1_up_tim16, /* [25] TIM1 Update Interrupt and TIM16 global interrupt */
[TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
[TIM1_CC_IRQn ] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */
[TIM2_IRQn ] = isr_tim2, /* [28] TIM2 global Interrupt */
[TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */
[TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */
[I2C1_EV_IRQn ] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */
[I2C1_ER_IRQn ] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */
[I2C2_EV_IRQn ] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */
[I2C2_ER_IRQn ] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */
[SPI1_IRQn ] = isr_spi1, /* [35] SPI1 global Interrupt */
[SPI2_IRQn ] = isr_spi2, /* [36] SPI2 global Interrupt */
[USART1_IRQn ] = isr_usart1, /* [37] USART1 global Interrupt */
[USART2_IRQn ] = isr_usart2, /* [38] USART2 global Interrupt */
[USART3_IRQn ] = isr_usart3, /* [39] USART3 global Interrupt */
[EXTI15_10_IRQn ] = isr_exti, /* [40] External Line[15:10] Interrupts */
[RTC_Alarm_IRQn ] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */
[USBWakeUp_IRQn ] = isr_usbwakeup, /* [42] USB Wakeup through EXTI line Interrupt */
[TIM8_BRK_IRQn ] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */
[TIM8_UP_IRQn ] = isr_tim8_up, /* [44] TIM8 Update Interrupt */
[TIM8_TRG_COM_IRQn ] = isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */
[TIM8_CC_IRQn ] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */
[ADC3_IRQn ] = isr_adc3, /* [47] ADC3 global Interrupt */
[FMC_IRQn ] = isr_fmc, /* [48] FMC global Interrupt */
[LPTIM1_IRQn ] = isr_lptim1, /* [49] LP TIM1 Interrupt */
[TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */
[SPI3_IRQn ] = isr_spi3, /* [51] SPI3 global Interrupt */
[UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */
[UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */
[TIM6_DAC_IRQn ] = isr_tim6_dac, /* [54] TIM6 global and DAC1&3 underrun error interrupts */
[TIM7_DAC_IRQn ] = isr_tim7_dac, /* [55] TIM7 global and DAC2&4 underrun error interrupts */
[DMA2_Channel1_IRQn ] = isr_dma2_channel1, /* [56] DMA2 Channel 1 global Interrupt */
[DMA2_Channel2_IRQn ] = isr_dma2_channel2, /* [57] DMA2 Channel 2 global Interrupt */
[DMA2_Channel3_IRQn ] = isr_dma2_channel3, /* [58] DMA2 Channel 3 global Interrupt */
[DMA2_Channel4_IRQn ] = isr_dma2_channel4, /* [59] DMA2 Channel 4 global Interrupt */
[DMA2_Channel5_IRQn ] = isr_dma2_channel5, /* [60] DMA2 Channel 5 global Interrupt */
[ADC4_IRQn ] = isr_adc4, /* [61] ADC4 global Interrupt */
[ADC5_IRQn ] = isr_adc5, /* [62] ADC5 global Interrupt */
[UCPD1_IRQn ] = isr_ucpd1, /* [63] UCPD global Interrupt */
[COMP1_2_3_IRQn ] = isr_comp1_2_3, /* [64] COMP1, COMP2 and COMP3 Interrupt */
[COMP4_5_6_IRQn ] = isr_comp4_5_6, /* [65] COMP4, COMP5 and Interrupt */
[COMP7_IRQn ] = isr_comp7, /* [66] COMP7 Interrupt */
[HRTIM1_Master_IRQn ] = isr_hrtim1_master, /* [67] HRTIM Master Timer global Interrupt */
[HRTIM1_TIMA_IRQn ] = isr_hrtim1_tima, /* [68] HRTIM Timer A global Interrupt */
[HRTIM1_TIMB_IRQn ] = isr_hrtim1_timb, /* [69] HRTIM Timer B global Interrupt */
[HRTIM1_TIMC_IRQn ] = isr_hrtim1_timc, /* [70] HRTIM Timer C global Interrupt */
[HRTIM1_TIMD_IRQn ] = isr_hrtim1_timd, /* [71] HRTIM Timer D global Interrupt */
[HRTIM1_TIME_IRQn ] = isr_hrtim1_time, /* [72] HRTIM Timer E global Interrupt */
[HRTIM1_FLT_IRQn ] = isr_hrtim1_flt, /* [73] HRTIM Fault global Interrupt */
[HRTIM1_TIMF_IRQn ] = isr_hrtim1_timf, /* [74] HRTIM Timer F global Interrupt */
[CRS_IRQn ] = isr_crs, /* [75] CRS global Interrupt */
[SAI1_IRQn ] = isr_sai1, /* [76] Serial Audio Interface global Interrupt */
[TIM20_BRK_IRQn ] = isr_tim20_brk, /* [77] TIM20 Break, Transition error and Index error Interrupt */
[TIM20_UP_IRQn ] = isr_tim20_up, /* [78] TIM20 Update Interrupt */
[TIM20_TRG_COM_IRQn ] = isr_tim20_trg_com, /* [79] TIM20 Trigger, Commutation, Direction change and Index Interrupt */
[TIM20_CC_IRQn ] = isr_tim20_cc, /* [80] TIM20 Capture Compare Interrupt */
[FPU_IRQn ] = isr_fpu, /* [81] FPU global Interrupt */
[I2C4_EV_IRQn ] = isr_i2c4_ev, /* [82] I2C4 Event Interrupt */
[I2C4_ER_IRQn ] = isr_i2c4_er, /* [83] I2C4 Error Interrupt */
[SPI4_IRQn ] = isr_spi4, /* [84] SPI4 Event Interrupt */
[FDCAN2_IT0_IRQn ] = isr_fdcan2_it0, /* [86] FDCAN2 interrupt line 0 Interrupt */
[FDCAN2_IT1_IRQn ] = isr_fdcan2_it1, /* [87] FDCAN2 interrupt line 1 Interrupt */
[FDCAN3_IT0_IRQn ] = isr_fdcan3_it0, /* [88] FDCAN3 interrupt line 0 Interrupt */
[FDCAN3_IT1_IRQn ] = isr_fdcan3_it1, /* [89] FDCAN3 interrupt line 1 Interrupt */
[RNG_IRQn ] = isr_rng, /* [90] RNG global Interrupt */
[LPUART1_IRQn ] = isr_lpuart1, /* [91] LP UART 1 Interrupt */
[I2C3_EV_IRQn ] = isr_i2c3_ev, /* [92] I2C3 Event Interrupt */
[I2C3_ER_IRQn ] = isr_i2c3_er, /* [93] I2C3 Error Interrupt */
[DMAMUX_OVR_IRQn ] = isr_dmamux, /* [94] DMAMUX overrun global Interrupt */
[QUADSPI_IRQn ] = isr_quadspi, /* [95] QUADSPI Interrupt */
[DMA1_Channel8_IRQn ] = isr_dma1_channel8, /* [96] DMA1 Channel 8 Interrupt */
[DMA2_Channel6_IRQn ] = isr_dma2_channel6, /* [97] DMA2 Channel 6 Interrupt */
[DMA2_Channel7_IRQn ] = isr_dma2_channel7, /* [98] DMA2 Channel 7 Interrupt */
[DMA2_Channel8_IRQn ] = isr_dma2_channel8, /* [99] DMA2 Channel 8 Interrupt */
[CORDIC_IRQn ] = isr_cordic, /* [100] CORDIC global Interrupt */
[FMAC_IRQn ] = isr_fmac, /* [101] FMAC global Interrupt */
};