diff --git a/boards/common/stm32/Kconfig.g0 b/boards/common/stm32/Kconfig.g0
index c7af0754ea..67a6b110bc 100644
--- a/boards/common/stm32/Kconfig.g0
+++ b/boards/common/stm32/Kconfig.g0
@@ -24,28 +24,25 @@ config USE_CLOCK_HSI
 
 endchoice
 
-if USE_CLOCK_PLL
 config CLOCK_PLL_M
-    int "M: PLLIN division factor"
+    int "M: PLLIN division factor" if USE_CLOCK_PLL
     default 1
     range 1 8
 
 config CLOCK_PLL_N
-    int "N: PLLIN multiply factor"
+    int "N: PLLIN multiply factor" if USE_CLOCK_PLL
     default 20
     range 8 86
 
 config CLOCK_PLL_R
-    int "Q: VCO division factor"
+    int "Q: VCO division factor" if USE_CLOCK_PLL
     default 6 if BOARD_HAS_HSE
-    default 5 if !BOARD_HAS_HSE
+    default 5
     range 2 8
-endif
 
 choice
-bool "HSISYS division factor"
+bool "HSISYS division factor" if USE_CLOCK_HSI
 default CLOCK_HSISYS_DIV_1
-depends on USE_CLOCK_HSI
 
 config CLOCK_HSISYS_DIV_1
     bool "Divide HSISYS by 1"
@@ -75,7 +72,7 @@ endchoice
 
 config CLOCK_HSISYS_DIV
     int
-    default 1 if CLOCK_HSISYS_DIV_1
+    default 1
     default 2 if CLOCK_HSISYS_DIV_2
     default 4 if CLOCK_HSISYS_DIV_4
     default 8 if CLOCK_HSISYS_DIV_8
diff --git a/boards/common/stm32/Kconfig.g4 b/boards/common/stm32/Kconfig.g4
index 3c5b660801..85baa9e913 100644
--- a/boards/common/stm32/Kconfig.g4
+++ b/boards/common/stm32/Kconfig.g4
@@ -24,20 +24,19 @@ config USE_CLOCK_HSI
 
 endchoice
 
-if USE_CLOCK_PLL
 config CLOCK_PLL_M
-    int "M: Division factor for the main PLL input clock"
+    int "M: Division factor for the main PLL input clock" if USE_CLOCK_PLL
     default 6 if BOARD_HAS_HSE
-    default 4 if !BOARD_HAS_HSE
+    default 4
     range 1 16
 
 config CLOCK_PLL_N
-    int "N: Multiply factor for the VCO"
+    int "N: Multiply factor for the VCO" if USE_CLOCK_PLL
     default 40
     range 8 127
 
 choice
-bool "R: Main PLL division factor for PLL 'R' clock (system clock)"
+bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if USE_CLOCK_PLL
 default PLL_R_DIV_2
 
 config PLL_R_DIV_2
@@ -60,7 +59,6 @@ config CLOCK_PLL_R
     default 4 if PLL_R_DIV_4
     default 6 if PLL_R_DIV_6
     default 8 if PLL_R_DIV_8
-endif
 
 choice
 bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"