From 9c46a4000507ef687c97f1bdc95e180f72d44ca1 Mon Sep 17 00:00:00 2001 From: haukepetersen Date: Mon, 15 Jun 2015 22:49:56 +0200 Subject: [PATCH 1/7] cpu: renamed nrf51822 to nrf51 --- cpu/{nrf51822 => nrf51}/Makefile | 0 cpu/{nrf51822 => nrf51}/Makefile.include | 0 cpu/{nrf51822 => nrf51}/cpu.c | 0 cpu/{nrf51822 => nrf51}/hwtimer_arch.c | 0 cpu/{nrf51822 => nrf51}/include/cpu_conf.h | 0 cpu/{nrf51822 => nrf51}/include/hwtimer_cpu.h | 0 cpu/{nrf51822 => nrf51}/include/nrf51.h | 0 cpu/{nrf51822 => nrf51}/include/nrf51_bitfields.h | 0 cpu/{nrf51822 => nrf51}/include/nrfmin.h | 0 cpu/{nrf51822 => nrf51}/include/periph_cpu.h | 0 cpu/{nrf51822 => nrf51}/ldscripts/nrf51822qfaa.ld | 0 cpu/{nrf51822 => nrf51}/lpm_arch.c | 0 cpu/{nrf51822 => nrf51}/periph/Makefile | 0 cpu/{nrf51822 => nrf51}/periph/cpuid.c | 0 cpu/{nrf51822 => nrf51}/periph/gpio.c | 0 cpu/{nrf51822 => nrf51}/periph/random.c | 0 cpu/{nrf51822 => nrf51}/periph/rtt.c | 0 cpu/{nrf51822 => nrf51}/periph/spi.c | 0 cpu/{nrf51822 => nrf51}/periph/timer.c | 0 cpu/{nrf51822 => nrf51}/periph/uart.c | 0 cpu/{nrf51822 => nrf51}/radio/nrfmin/Makefile | 0 cpu/{nrf51822 => nrf51}/radio/nrfmin/nrfmin.c | 0 cpu/{nrf51822 => nrf51}/vectors.c | 0 23 files changed, 0 insertions(+), 0 deletions(-) rename cpu/{nrf51822 => nrf51}/Makefile (100%) rename cpu/{nrf51822 => nrf51}/Makefile.include (100%) rename cpu/{nrf51822 => nrf51}/cpu.c (100%) rename cpu/{nrf51822 => nrf51}/hwtimer_arch.c (100%) rename cpu/{nrf51822 => nrf51}/include/cpu_conf.h (100%) rename cpu/{nrf51822 => nrf51}/include/hwtimer_cpu.h (100%) rename cpu/{nrf51822 => nrf51}/include/nrf51.h (100%) rename cpu/{nrf51822 => nrf51}/include/nrf51_bitfields.h (100%) rename cpu/{nrf51822 => nrf51}/include/nrfmin.h (100%) rename cpu/{nrf51822 => nrf51}/include/periph_cpu.h (100%) rename cpu/{nrf51822 => nrf51}/ldscripts/nrf51822qfaa.ld (100%) rename cpu/{nrf51822 => nrf51}/lpm_arch.c (100%) rename cpu/{nrf51822 => nrf51}/periph/Makefile (100%) rename cpu/{nrf51822 => nrf51}/periph/cpuid.c (100%) rename cpu/{nrf51822 => nrf51}/periph/gpio.c (100%) rename cpu/{nrf51822 => nrf51}/periph/random.c (100%) rename cpu/{nrf51822 => nrf51}/periph/rtt.c (100%) rename cpu/{nrf51822 => nrf51}/periph/spi.c (100%) rename cpu/{nrf51822 => nrf51}/periph/timer.c (100%) rename cpu/{nrf51822 => nrf51}/periph/uart.c (100%) rename cpu/{nrf51822 => nrf51}/radio/nrfmin/Makefile (100%) rename cpu/{nrf51822 => nrf51}/radio/nrfmin/nrfmin.c (100%) rename cpu/{nrf51822 => nrf51}/vectors.c (100%) diff --git a/cpu/nrf51822/Makefile b/cpu/nrf51/Makefile similarity index 100% rename from cpu/nrf51822/Makefile rename to cpu/nrf51/Makefile diff --git a/cpu/nrf51822/Makefile.include b/cpu/nrf51/Makefile.include similarity index 100% rename from cpu/nrf51822/Makefile.include rename to cpu/nrf51/Makefile.include diff --git a/cpu/nrf51822/cpu.c b/cpu/nrf51/cpu.c similarity index 100% rename from cpu/nrf51822/cpu.c rename to cpu/nrf51/cpu.c diff --git a/cpu/nrf51822/hwtimer_arch.c b/cpu/nrf51/hwtimer_arch.c similarity index 100% rename from cpu/nrf51822/hwtimer_arch.c rename to cpu/nrf51/hwtimer_arch.c diff --git a/cpu/nrf51822/include/cpu_conf.h b/cpu/nrf51/include/cpu_conf.h similarity index 100% rename from cpu/nrf51822/include/cpu_conf.h rename to cpu/nrf51/include/cpu_conf.h diff --git a/cpu/nrf51822/include/hwtimer_cpu.h b/cpu/nrf51/include/hwtimer_cpu.h similarity index 100% rename from cpu/nrf51822/include/hwtimer_cpu.h rename to cpu/nrf51/include/hwtimer_cpu.h diff --git a/cpu/nrf51822/include/nrf51.h b/cpu/nrf51/include/nrf51.h similarity index 100% rename from cpu/nrf51822/include/nrf51.h rename to cpu/nrf51/include/nrf51.h diff --git a/cpu/nrf51822/include/nrf51_bitfields.h b/cpu/nrf51/include/nrf51_bitfields.h similarity index 100% rename from cpu/nrf51822/include/nrf51_bitfields.h rename to cpu/nrf51/include/nrf51_bitfields.h diff --git a/cpu/nrf51822/include/nrfmin.h b/cpu/nrf51/include/nrfmin.h similarity index 100% rename from cpu/nrf51822/include/nrfmin.h rename to cpu/nrf51/include/nrfmin.h diff --git a/cpu/nrf51822/include/periph_cpu.h b/cpu/nrf51/include/periph_cpu.h similarity index 100% rename from cpu/nrf51822/include/periph_cpu.h rename to cpu/nrf51/include/periph_cpu.h diff --git a/cpu/nrf51822/ldscripts/nrf51822qfaa.ld b/cpu/nrf51/ldscripts/nrf51822qfaa.ld similarity index 100% rename from cpu/nrf51822/ldscripts/nrf51822qfaa.ld rename to cpu/nrf51/ldscripts/nrf51822qfaa.ld diff --git a/cpu/nrf51822/lpm_arch.c b/cpu/nrf51/lpm_arch.c similarity index 100% rename from cpu/nrf51822/lpm_arch.c rename to cpu/nrf51/lpm_arch.c diff --git a/cpu/nrf51822/periph/Makefile b/cpu/nrf51/periph/Makefile similarity index 100% rename from cpu/nrf51822/periph/Makefile rename to cpu/nrf51/periph/Makefile diff --git a/cpu/nrf51822/periph/cpuid.c b/cpu/nrf51/periph/cpuid.c similarity index 100% rename from cpu/nrf51822/periph/cpuid.c rename to cpu/nrf51/periph/cpuid.c diff --git a/cpu/nrf51822/periph/gpio.c b/cpu/nrf51/periph/gpio.c similarity index 100% rename from cpu/nrf51822/periph/gpio.c rename to cpu/nrf51/periph/gpio.c diff --git a/cpu/nrf51822/periph/random.c b/cpu/nrf51/periph/random.c similarity index 100% rename from cpu/nrf51822/periph/random.c rename to cpu/nrf51/periph/random.c diff --git a/cpu/nrf51822/periph/rtt.c b/cpu/nrf51/periph/rtt.c similarity index 100% rename from cpu/nrf51822/periph/rtt.c rename to cpu/nrf51/periph/rtt.c diff --git a/cpu/nrf51822/periph/spi.c b/cpu/nrf51/periph/spi.c similarity index 100% rename from cpu/nrf51822/periph/spi.c rename to cpu/nrf51/periph/spi.c diff --git a/cpu/nrf51822/periph/timer.c b/cpu/nrf51/periph/timer.c similarity index 100% rename from cpu/nrf51822/periph/timer.c rename to cpu/nrf51/periph/timer.c diff --git a/cpu/nrf51822/periph/uart.c b/cpu/nrf51/periph/uart.c similarity index 100% rename from cpu/nrf51822/periph/uart.c rename to cpu/nrf51/periph/uart.c diff --git a/cpu/nrf51822/radio/nrfmin/Makefile b/cpu/nrf51/radio/nrfmin/Makefile similarity index 100% rename from cpu/nrf51822/radio/nrfmin/Makefile rename to cpu/nrf51/radio/nrfmin/Makefile diff --git a/cpu/nrf51822/radio/nrfmin/nrfmin.c b/cpu/nrf51/radio/nrfmin/nrfmin.c similarity index 100% rename from cpu/nrf51822/radio/nrfmin/nrfmin.c rename to cpu/nrf51/radio/nrfmin/nrfmin.c diff --git a/cpu/nrf51822/vectors.c b/cpu/nrf51/vectors.c similarity index 100% rename from cpu/nrf51822/vectors.c rename to cpu/nrf51/vectors.c From 987dbe983abec1c4b934b2bcd98f5922d0d11549 Mon Sep 17 00:00:00 2001 From: haukepetersen Date: Mon, 15 Jun 2015 23:02:16 +0200 Subject: [PATCH 2/7] cpu/nrf51: generalized linkerscript --- cpu/nrf51/ldscripts/{nrf51822qfaa.ld => nrf51x22xxaa.ld} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename cpu/nrf51/ldscripts/{nrf51822qfaa.ld => nrf51x22xxaa.ld} (89%) diff --git a/cpu/nrf51/ldscripts/nrf51822qfaa.ld b/cpu/nrf51/ldscripts/nrf51x22xxaa.ld similarity index 89% rename from cpu/nrf51/ldscripts/nrf51822qfaa.ld rename to cpu/nrf51/ldscripts/nrf51x22xxaa.ld index 1953dbb8a2..72023d26aa 100644 --- a/cpu/nrf51/ldscripts/nrf51822qfaa.ld +++ b/cpu/nrf51/ldscripts/nrf51x22xxaa.ld @@ -11,7 +11,7 @@ * @{ * * @file - * @brief Memory definitions for the NRF51822QFAA + * @brief Memory definitions for the NRF51X22XXAA * * @author Hauke Petersen * From 431ac7b3c559fb76dbfd13bbd3b572ca5299c670 Mon Sep 17 00:00:00 2001 From: haukepetersen Date: Mon, 15 Jun 2015 23:02:43 +0200 Subject: [PATCH 3/7] cpu/nrf51: added linkerscript for 128kb variant --- cpu/nrf51/ldscripts/nrf51x22xxab.ld | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 cpu/nrf51/ldscripts/nrf51x22xxab.ld diff --git a/cpu/nrf51/ldscripts/nrf51x22xxab.ld b/cpu/nrf51/ldscripts/nrf51x22xxab.ld new file mode 100644 index 0000000000..b72c9324ff --- /dev/null +++ b/cpu/nrf51/ldscripts/nrf51x22xxab.ld @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @addtogroup cpu_nrf51822 + * @{ + * + * @file + * @brief Memory definitions for the NRF51X22XXAB + * + * @author Hauke Petersen + * + * @} + */ + +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +INCLUDE cortexm_base.ld From 376934bc0ad2550cdf3d7a20b34e8d23ab97dc39 Mon Sep 17 00:00:00 2001 From: haukepetersen Date: Mon, 15 Jun 2015 23:03:29 +0200 Subject: [PATCH 4/7] boards: adapted nrf51 based boards to new CPU name --- boards/airfy-beacon/Makefile.include | 6 +++--- boards/pca10000/Makefile.include | 7 ++++--- boards/pca10005/Makefile.include | 8 ++++---- boards/yunjia-nrf51822/Makefile.include | 6 +++--- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/boards/airfy-beacon/Makefile.include b/boards/airfy-beacon/Makefile.include index 290d5b4a43..f6d5be3298 100644 --- a/boards/airfy-beacon/Makefile.include +++ b/boards/airfy-beacon/Makefile.include @@ -1,6 +1,6 @@ -# define the cpu used by the airfy-beacon board -export CPU = nrf51822 -export CPU_MODEL = nrf51822qfaa +# define the used CPU +export CPU = nrf51 +export CPU_MODEL = nrf51x22xxaa # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyUSB0 diff --git a/boards/pca10000/Makefile.include b/boards/pca10000/Makefile.include index 428f45eb2b..04bfc45d9e 100644 --- a/boards/pca10000/Makefile.include +++ b/boards/pca10000/Makefile.include @@ -1,11 +1,12 @@ -# define the cpu used by the nRF51822 board pca10000 -export CPU = nrf51822 -export CPU_MODEL = nrf51822qfaa +# define the used CPU +export CPU = nrf51 +export CPU_MODEL = nrf51x22xxaa # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyACM0 PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1) +# define flash and debugging environment export FLASHER = $(RIOTBOARD)/$(BOARD)/dist/flash.sh export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh export DEBUGSERVER = JLinkGDBServer -device nrf51822 -if SWD diff --git a/boards/pca10005/Makefile.include b/boards/pca10005/Makefile.include index 6d0267045a..6293664add 100644 --- a/boards/pca10005/Makefile.include +++ b/boards/pca10005/Makefile.include @@ -1,12 +1,12 @@ -# define the cpu used by the nRF51822 board pca10005 -export CPU = nrf51822 -export CPU_MODEL = nrf51822qfaa +# define the used CPU +export CPU = nrf51 +export CPU_MODEL = nrf51x22xxaa # set default port depending on operating system PORT_LINUX ?= /dev/ttyUSB0 PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1) -# +# define flash and debugging environment export FLASHER = $(RIOTBOARD)/$(BOARD)/dist/flash.sh export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh export DEBUGSERVER = JLinkGDBServer -device nrf51822 -if SWD diff --git a/boards/yunjia-nrf51822/Makefile.include b/boards/yunjia-nrf51822/Makefile.include index a4a8d7a70e..f6d5be3298 100644 --- a/boards/yunjia-nrf51822/Makefile.include +++ b/boards/yunjia-nrf51822/Makefile.include @@ -1,6 +1,6 @@ -# define the cpu used by the yunjia-nrf51822 board -export CPU = nrf51822 -export CPU_MODEL = nrf51822qfaa +# define the used CPU +export CPU = nrf51 +export CPU_MODEL = nrf51x22xxaa # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyUSB0 From 1cd18f92c93c7209965c5e80085f6dd2ad7447b0 Mon Sep 17 00:00:00 2001 From: haukepetersen Date: Mon, 15 Jun 2015 23:16:50 +0200 Subject: [PATCH 5/7] cpu/nrf51: updated CPU headers --- cpu/nrf51/include/nrf51.h | 150 +++++++++++---- cpu/nrf51/include/nrf51_bitfields.h | 283 +++++++++++++++++++++++----- 2 files changed, 340 insertions(+), 93 deletions(-) diff --git a/cpu/nrf51/include/nrf51.h b/cpu/nrf51/include/nrf51.h index 7459ab2135..9c98da12b3 100644 --- a/cpu/nrf51/include/nrf51.h +++ b/cpu/nrf51/include/nrf51.h @@ -1,15 +1,15 @@ -/****************************************************************************************************/ -/** - * @file + +/****************************************************************************************************//** + * @file nrf51.h * * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for - * nRF51 from Nordic Semiconductor. + * nrf51 from Nordic Semiconductor. * * @version V522 - * @date 4. March 2014 + * @date 29. April 2015 * - * @note Generated with SVDConv V2.77p - * from CMSIS SVD File 'nRF51.xml' Version 522, + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf51.xml' Version 522, * * @par Copyright (c) 2013, Nordic Semiconductor ASA * All rights reserved. @@ -44,11 +44,11 @@ -/** @addtogroup cpu_specific_Nordic Semiconductor +/** @addtogroup Nordic Semiconductor * @{ */ -/** @addtogroup cpu_specific_nRF51 +/** @addtogroup nrf51 * @{ */ @@ -71,7 +71,7 @@ typedef enum { DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */ +/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ RADIO_IRQn = 1, /*!< 1 RADIO */ UART0_IRQn = 2, /*!< 2 UART0 */ @@ -109,29 +109,22 @@ typedef enum { /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ -/* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */ +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** @} */ /* End of group Configuration_of_CMSIS */ -#ifdef __cplusplus -} -#endif +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include /*!< Cortex-M0 processor and core peripherals */ - -#ifdef __cplusplus -extern "C" { -#endif /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ /* ================================================================================ */ -/** @addtogroup cpu_specific_Device_Peripheral_Registers +/** @addtogroup Device_Peripheral_Registers * @{ */ @@ -162,6 +155,24 @@ typedef struct { __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ } AMLI_RAMPRI_Type; +typedef struct { + __IO uint32_t SCK; /*!< Pin select for SCK. */ + __IO uint32_t MOSI; /*!< Pin select for MOSI. */ + __IO uint32_t MISO; /*!< Pin select for MISO. */ +} SPIM_PSEL_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ + __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ +} SPIM_RXD_Type; + +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ + __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ +} SPIM_TXD_Type; + typedef struct { __O uint32_t EN; /*!< Enable channel group. */ __O uint32_t DIS; /*!< Disable channel group. */ @@ -277,8 +288,6 @@ typedef struct { /*!< MPU Structure __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ - __I uint32_t RESERVED2[255]; - __IO uint32_t ENRBDREG; /*!< Enable or disable RBD. */ } NRF_MPU_Type; @@ -348,7 +357,7 @@ typedef struct { /*!< RADIO Structure __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI sample is ready for readout at the RSSISAMPLE register. */ __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */ + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */ __I uint32_t RESERVED2[53]; __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ __I uint32_t RESERVED3[64]; @@ -425,29 +434,27 @@ typedef struct { /*!< UART Structure __IO uint32_t EVENTS_ERROR; /*!< Error detected. */ __I uint32_t RESERVED4[7]; __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ - __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ - __I uint32_t RESERVED6[64]; + __I uint32_t RESERVED5[111]; __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED7[93]; + __I uint32_t RESERVED6[93]; __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED8[31]; + __I uint32_t RESERVED7[31]; __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */ - __I uint32_t RESERVED9; + __I uint32_t RESERVED8; __IO uint32_t PSELRTS; /*!< Pin select for RTS. */ __IO uint32_t PSELTXD; /*!< Pin select for TXD. */ __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. - Once read the character is consummed. If read when no character + Once read the character is consumed. If read when no character available, the UART will stop working. */ __O uint32_t TXD; /*!< TXD register. */ - __I uint32_t RESERVED10; + __I uint32_t RESERVED9; __IO uint32_t BAUDRATE; /*!< UART Baudrate. */ - __I uint32_t RESERVED11[17]; + __I uint32_t RESERVED10[17]; __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */ - __I uint32_t RESERVED12[675]; + __I uint32_t RESERVED11[675]; __IO uint32_t POWER; /*!< Peripheral power control. */ } NRF_UART_Type; @@ -590,6 +597,56 @@ typedef struct { /*!< SPIS Structure } NRF_SPIS_Type; +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI master with easyDMA 1. (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction. */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED9[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM. */ + __I uint32_t RESERVED10; + SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */ + __I uint32_t RESERVED11[4]; + __IO uint32_t FREQUENCY; /*!< SPI frequency. */ + __I uint32_t RESERVED12[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */ + __I uint32_t RESERVED13; + SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */ + __I uint32_t RESERVED14; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED15[26]; + __IO uint32_t ORC; /*!< Over-read character. */ + __I uint32_t RESERVED16[654]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPIM_Type; + + /* ================================================================================ */ /* ================ GPIOTE ================ */ /* ================================================================================ */ @@ -1016,9 +1073,13 @@ typedef struct { /*!< NVMC Structure __I uint32_t READY; /*!< Ready flag. */ __I uint32_t RESERVED1[64]; __IO uint32_t CONFIG; /*!< Configuration register. */ - __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */ + + union { + __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */ + }; __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */ - __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */ + __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */ __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */ } NRF_NVMC_Type; @@ -1058,8 +1119,7 @@ typedef struct { /*!< FICR Structure __I uint32_t RESERVED0[4]; __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */ __I uint32_t CODESIZE; /*!< Code memory size in pages. */ - __I uint32_t RBD; /*!< RBD. */ - __I uint32_t RESERVED1[3]; + __I uint32_t RESERVED1[4]; __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */ __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ __I uint32_t RESERVED2; @@ -1070,7 +1130,7 @@ typedef struct { /*!< FICR Structure kept for backward compatinility purposes. Use SIZERAMBLOCKS instead. */ __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ - } ; + }; __I uint32_t RESERVED3[5]; __I uint32_t CONFIGID; /*!< Configuration identifier. */ __I uint32_t DEVICEID[2]; /*!< Device identifier. */ @@ -1103,7 +1163,13 @@ typedef struct { /*!< UICR Structure __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */ __I uint32_t RESERVED0; __I uint32_t FWID; /*!< Firmware ID. */ - __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */ + + union { + __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ + __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */ + }; + __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ + __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ } NRF_UICR_Type; @@ -1164,6 +1230,7 @@ typedef struct { /*!< GPIO Structure #define NRF_SPI1_BASE 0x40004000UL #define NRF_TWI1_BASE 0x40004000UL #define NRF_SPIS1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL #define NRF_GPIOTE_BASE 0x40006000UL #define NRF_ADC_BASE 0x40007000UL #define NRF_TIMER0_BASE 0x40008000UL @@ -1203,6 +1270,7 @@ typedef struct { /*!< GPIO Structure #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) @@ -1227,11 +1295,11 @@ typedef struct { /*!< GPIO Structure /** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group nRF51 */ +/** @} */ /* End of group nrf51 */ /** @} */ /* End of group Nordic Semiconductor */ #ifdef __cplusplus } #endif -#endif /* nRF51_H */ +#endif /* nrf51_H */ diff --git a/cpu/nrf51/include/nrf51_bitfields.h b/cpu/nrf51/include/nrf51_bitfields.h index 8cd0937652..1bcdb7269c 100644 --- a/cpu/nrf51/include/nrf51_bitfields.h +++ b/cpu/nrf51/include/nrf51_bitfields.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA +/* Copyright (c) 2015, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,14 +30,12 @@ #ifndef __NRF51_BITS_H #define __NRF51_BITS_H -/*lint ++flb "Enter library region */ - -#include - #ifdef __cplusplus -extern "C" { + extern "C" { #endif +/*lint ++flb "Enter library region" */ + /* Peripheral: AAR */ /* Description: Accelerated Address Resolver. */ @@ -824,6 +822,7 @@ extern "C" { #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption. */ @@ -1068,8 +1067,8 @@ extern "C" { /* Bits 7..0 : External Xtal frequency selection. */ #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ +#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ /* Peripheral: ECB */ @@ -1122,23 +1121,14 @@ extern "C" { /* Peripheral: FICR */ /* Description: Factory Information Configuration. */ -/* Register: FICR_RBD */ -/* Description: RBD. */ - -/* Bits 31..0 : RBD. */ -#define FICR_RBD_RBD_Pos (0UL) /*!< Position of RBD field. */ -#define FICR_RBD_RBD_Msk (0xFFFFFFFFUL << FICR_RBD_RBD_Pos) /*!< Bit mask of RBD field. */ -#define FICR_RBD_RBD_NoRoyalty (0xFFFFFFFEUL) /*!< No royalty. */ -#define FICR_RBD_RBD_Royalty (0xFFFFFFFFUL) /*!< Royalty. */ - /* Register: FICR_PPFC */ /* Description: Pre-programmed factory code present. */ /* Bits 7..0 : Pre-programmed factory code present. */ #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ -#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ +#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ /* Register: FICR_CONFIGID */ /* Description: Configuration identifier. */ @@ -2805,6 +2795,7 @@ extern "C" { /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */ #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ @@ -3608,15 +3599,6 @@ extern "C" { #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ -/* Register: MPU_ENRBDREG */ -/* Description: Enable or disable RBD. */ - -/* Bit 0 : Enable or disable RBD. */ -#define MPU_ENRBDREG_ENRBDREG_Pos (0UL) /*!< Position of ENRBDREG field. */ -#define MPU_ENRBDREG_ENRBDREG_Msk (0x1UL << MPU_ENRBDREG_ENRBDREG_Pos) /*!< Bit mask of ENRBDREG field. */ -#define MPU_ENRBDREG_ENRBDREG_Disabled (0UL) /*!< RBD disabled. */ -#define MPU_ENRBDREG_ENRBDREG_Enabled (1UL) /*!< RBD enabled. */ - /* Peripheral: NVMC */ /* Description: Non Volatile Memory Controller. */ @@ -3688,30 +3670,44 @@ extern "C" { /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */ /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */ /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */ /* Bit 3 : Reset from CPU lock-up detected. */ #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */ /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */ /* Bit 1 : Reset from watchdog detected. */ #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */ /* Bit 0 : Reset from pin-reset detected. */ #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */ /* Register: POWER_RAMSTATUS */ /* Description: Ram status register. */ @@ -5181,14 +5177,14 @@ extern "C" { /* Bits 7..0 : Radio output power. Decision point: TXEN task. */ #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation. */ @@ -5965,6 +5961,197 @@ extern "C" { #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +/* Peripheral: SPIM */ +/* Description: SPI master with easyDMA 1. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts for SPIM. */ + +/* Bit 17 : Shortcut between END event and START task. */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on STARTED event. */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 8 : Enable interrupt on ENDTX event. */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on END event. */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on ENDRX event. */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on STARTED event. */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 8 : Disable interrupt on ENDTX event. */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on END event. */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM. */ + +/* Bits 3..0 : Enable or disable SPIM. */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ +#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. */ + +/* Bits 31..0 : SPI master data rate. */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to receive. */ + +/* Bits 7..0 : Maximum number of buffer bytes to receive. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes received in the last transaction. */ + +/* Bits 7..0 : Number of bytes received in the last transaction. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to send. */ + +/* Bits 7..0 : Maximum number of buffer bytes to send. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes sent in the last transaction. */ + +/* Bits 7..0 : Number of bytes sent in the last transaction. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + /* Peripheral: SPIS */ /* Description: SPI slave 1. */ @@ -6432,6 +6619,13 @@ extern "C" { #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ +/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ + /* Register: TWI_ENABLE */ /* Description: Enable two-wire master. */ @@ -6485,21 +6679,6 @@ extern "C" { /* Peripheral: UART */ /* Description: Universal Asynchronous Receiver/Transmitter. */ -/* Register: UART_SHORTS */ -/* Description: Shortcuts for UART. */ - -/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ -#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between CTS event and the STARTRX task. */ -#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ - /* Register: UART_INTENSET */ /* Description: Interrupt enable set register. */ @@ -6631,7 +6810,7 @@ extern "C" { #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ /* Register: UART_RXD */ -/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */ +/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ /* Bits 7..0 : RX data from previous transfer. Double buffered. */ #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ @@ -6664,7 +6843,7 @@ extern "C" { #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ /* Register: UART_CONFIG */ @@ -6701,14 +6880,14 @@ extern "C" { /* Bits 15..8 : Readback protect all code in the device. */ #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ -#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ -#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ /* Register: UICR_XTALFREQ */ /* Description: Reset value for CLOCK XTALFREQ register. */ @@ -6716,8 +6895,8 @@ extern "C" { /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ +#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ /* Register: UICR_FWID */ /* Description: Firmware ID. */ From c7d4ff71065f606ef1e7038fe2952318b8e872c3 Mon Sep 17 00:00:00 2001 From: Hauke Petersen Date: Tue, 14 Jul 2015 17:21:30 +0200 Subject: [PATCH 6/7] doxygen: adjusted exclude pattern for NRF51 --- doc/doxygen/riot.doxyfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/doxygen/riot.doxyfile b/doc/doxygen/riot.doxyfile index a23d52dc51..5a81196ffb 100644 --- a/doc/doxygen/riot.doxyfile +++ b/doc/doxygen/riot.doxyfile @@ -822,7 +822,7 @@ EXCLUDE_PATTERNS = */board/*/tools/* \ */cpu/cortexm_common/include/core_cm*.h \ */cpu/stm32f*/include/stm32f* \ */drivers/nrf24l01p/include/nrf24l01p_settings.h \ - */cpu/nrf51822/include/nrf51.h \ + */cpu/nrf51/include/nrf51*.h \ */cpu/lpc1768/include/LPC17xx.h \ */boards/*/include/periph_conf.h \ */cpu/x86/include/x86_pci.h \ From 696dff5da32385f9a5cf84b249dbebd2a564c3f8 Mon Sep 17 00:00:00 2001 From: Hauke Petersen Date: Tue, 14 Jul 2015 18:22:03 +0200 Subject: [PATCH 7/7] cpu/nrf51: fixedd cppcheck issue in spi.c --- cpu/nrf51/periph/spi.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/cpu/nrf51/periph/spi.c b/cpu/nrf51/periph/spi.c index c52c7a2b3e..ceb5abae83 100644 --- a/cpu/nrf51/periph/spi.c +++ b/cpu/nrf51/periph/spi.c @@ -160,11 +160,6 @@ int spi_conf_pins(spi_t dev) return 0; } -int spi_transfer_byte(spi_t dev, char out, char *in) -{ - return spi_transfer_bytes(dev, &out, in, 1); -} - int spi_acquire(spi_t dev) { if (dev >= SPI_NUMOF) { @@ -183,16 +178,19 @@ int spi_release(spi_t dev) return 0; } +int spi_transfer_byte(spi_t dev, char out, char *in) +{ + return spi_transfer_bytes(dev, &out, in, 1); +} + int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length) { - char tmp; - if (dev >= SPI_NUMOF) { return -1; } for (int i = 0; i < length; i++) { - tmp = (out) ? out[i] : 0; + char tmp = (out) ? out[i] : 0; spi[dev]->EVENTS_READY = 0; spi[dev]->TXD = (uint8_t)tmp; while (spi[dev]->EVENTS_READY != 1);