diff --git a/boards/nucleo-f091/include/board.h b/boards/nucleo-f091/include/board.h index 3d13993d5f..6725b0bde9 100644 --- a/boards/nucleo-f091/include/board.h +++ b/boards/nucleo-f091/include/board.h @@ -16,6 +16,7 @@ * @brief Board specific definitions for the nucleo-f091 board * * @author Hauke Petersen + * @author Mohmmad Ayman */ #ifndef BOARD_H_ @@ -46,8 +47,8 @@ extern "C" { #define LED_RED_OFF #define LED_RED_TOGGLE -#define LED_GREEN_ON (LED_GREEN_PORT->BSRRL = (1 << LED_GREEN_PIN)) -#define LED_GREEN_OFF (LED_GREEN_PORT->BSRRH = (1 << LED_GREEN_PIN)) +#define LED_GREEN_ON (LED_GREEN_PORT->BSRR = (1 << LED_GREEN_PIN)) +#define LED_GREEN_OFF (LED_GREEN_PORT->BSRR = ((1 << LED_GREEN_PIN) << 16)) #define LED_GREEN_TOGGLE (LED_GREEN_PORT->ODR ^= (1 << LED_GREEN_PIN)) #define LED_ORANGE_ON diff --git a/boards/nucleo-f091/include/periph_conf.h b/boards/nucleo-f091/include/periph_conf.h index 578931409c..2fc290fb45 100644 --- a/boards/nucleo-f091/include/periph_conf.h +++ b/boards/nucleo-f091/include/periph_conf.h @@ -88,74 +88,6 @@ extern "C" { #define UART_1_AF 0 /** @} */ -/** - * @name GPIO configuration - * @{ - */ -#define GPIO_0_EN 1 -#define GPIO_1_EN 1 -#define GPIO_2_EN 1 -#define GPIO_3_EN 1 -#define GPIO_4_EN 1 -#define GPIO_5_EN 1 -#define GPIO_IRQ_PRIO 1 - -/* IRQ config */ -#define GPIO_IRQ_0 -1 /* not configured */ -#define GPIO_IRQ_1 -1 /* not configured */ -#define GPIO_IRQ_2 -1 /* not configured */ -#define GPIO_IRQ_3 -1 /* not configured */ -#define GPIO_IRQ_4 -1 /* not configured */ -#define GPIO_IRQ_5 -1 /* not configured */ -#define GPIO_IRQ_6 -1 /* not configured */ -#define GPIO_IRQ_7 -1 /* not configured */ -#define GPIO_IRQ_8 -1 /* not configured */ -#define GPIO_IRQ_9 -1 /* not configured */ -#define GPIO_IRQ_10 GPIO_0 -#define GPIO_IRQ_11 GPIO_1 -#define GPIO_IRQ_12 GPIO_2 -#define GPIO_IRQ_13 GPIO_3 -#define GPIO_IRQ_14 GPIO_4 -#define GPIO_IRQ_15 GPIO_5 - -/* GPIO channel 0 config */ -#define GPIO_0_PORT GPIOC -#define GPIO_0_PIN 10 -#define GPIO_0_CLK 19 -#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PC) -#define GPIO_0_IRQ EXTI4_15_IRQn -/* GPIO channel 1 config */ -#define GPIO_1_PORT GPIOC -#define GPIO_1_PIN 11 -#define GPIO_1_CLK 19 -#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PC) -#define GPIO_1_IRQ EXTI4_15_IRQn -/* GPIO channel 2 config */ -#define GPIO_2_PORT GPIOC -#define GPIO_2_PIN 12 -#define GPIO_2_CLK 19 -#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PC) -#define GPIO_2_IRQ EXTI4_15_IRQn -/* GPIO channel 3 config */ -#define GPIO_3_PORT GPIOC -#define GPIO_3_PIN 13 /* Used for user button 1 */ -#define GPIO_3_CLK 19 -#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PC) -#define GPIO_3_IRQ EXTI4_15_IRQn -/* GPIO channel 4 config */ -#define GPIO_4_PORT GPIOC -#define GPIO_4_PIN 14 -#define GPIO_4_CLK 19 -#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI14_PC) -#define GPIO_4_IRQ EXTI4_15_IRQn -/* GPIO channel 5 config */ -#define GPIO_5_PORT GPIOC -#define GPIO_5_PIN 15 -#define GPIO_5_CLK 19 -#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI15_PC) -#define GPIO_5_IRQ EXTI4_15_IRQn -/** @} */ - /** * @name RTC configuration * @{ diff --git a/boards/stm32f0discovery/include/board.h b/boards/stm32f0discovery/include/board.h index 4795b52c14..539db663df 100644 --- a/boards/stm32f0discovery/include/board.h +++ b/boards/stm32f0discovery/include/board.h @@ -40,11 +40,11 @@ extern "C" { * @name Macros for controlling the on-board LEDs. * @{ */ -#define LD3_ON (LED_PORT->BSRRL = LD3_PIN) -#define LD3_OFF (LED_PORT->BSRRH = LD3_PIN) +#define LD3_ON (LED_PORT->BSRR = LD3_PIN) +#define LD3_OFF (LED_PORT->BSRR = (LD3_PIN << 16)) #define LD3_TOGGLE (LED_PORT->ODR ^= LD3_PIN) -#define LD4_ON (LED_PORT->BSRRL = LD4_PIN) -#define LD4_OFF (LED_PORT->BSRRH = LD4_PIN) +#define LD4_ON (LED_PORT->BSRR = LD4_PIN) +#define LD4_OFF (LED_PORT->BSRR = (LD4_PIN << 16)) #define LD4_TOGGLE (LED_PORT->ODR ^= LD4_PIN) /* for compatibility to other boards */ diff --git a/boards/stm32f0discovery/include/periph_conf.h b/boards/stm32f0discovery/include/periph_conf.h index 3f19da395f..19be583e4b 100644 --- a/boards/stm32f0discovery/include/periph_conf.h +++ b/boards/stm32f0discovery/include/periph_conf.h @@ -161,116 +161,6 @@ extern "C" { #define SPI_1_PIN_AF 0 /** @} */ -/** - * @name GPIO configuration - * @{ - */ -#define GPIO_0_EN 1 -#define GPIO_1_EN 1 -#define GPIO_2_EN 1 -#define GPIO_3_EN 1 -#define GPIO_4_EN 1 -#define GPIO_5_EN 1 -#define GPIO_6_EN 1 -#define GPIO_7_EN 1 -#define GPIO_8_EN 1 -#define GPIO_9_EN 1 -#define GPIO_10_EN 1 -#define GPIO_11_EN 1 -#define GPIO_IRQ_PRIO 1 - -/* IRQ config */ -#define GPIO_IRQ_0 GPIO_0 -#define GPIO_IRQ_1 GPIO_1 -#define GPIO_IRQ_2 -1 /* not configured */ -#define GPIO_IRQ_3 -1 /* not configured */ -#define GPIO_IRQ_4 GPIO_2 -#define GPIO_IRQ_5 GPIO_3 -#define GPIO_IRQ_6 GPIO_4 -#define GPIO_IRQ_7 GPIO_5 -#define GPIO_IRQ_8 -1 /* not configured */ -#define GPIO_IRQ_9 -1 /* not configured */ -#define GPIO_IRQ_10 GPIO_6 -#define GPIO_IRQ_11 GPIO_7 -#define GPIO_IRQ_12 GPIO_8 -#define GPIO_IRQ_13 GPIO_9 -#define GPIO_IRQ_14 GPIO_10 -#define GPIO_IRQ_15 GPIO_11 - -/* GPIO channel 0 config */ -#define GPIO_0_PORT GPIOA /* Used for user button 1 */ -#define GPIO_0_PIN 0 -#define GPIO_0_CLK 17 /* 0: PORT A, 1: B ... */ -#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA) -#define GPIO_0_IRQ EXTI0_1_IRQn -/* GPIO channel 1 config */ -#define GPIO_1_PORT GPIOA -#define GPIO_1_PIN 1 -#define GPIO_1_CLK 17 -#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PA) -#define GPIO_1_IRQ EXTI0_1_IRQn -/* GPIO channel 2 config */ -#define GPIO_2_PORT GPIOF -#define GPIO_2_PIN 4 -#define GPIO_2_CLK 22 -#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PF) -#define GPIO_2_IRQ EXTI4_15_IRQn -/* GPIO channel 3 config */ -#define GPIO_3_PORT GPIOF -#define GPIO_3_PIN 5 -#define GPIO_3_CLK 22 -#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PF) -#define GPIO_3_IRQ EXTI4_15_IRQn -/* GPIO channel 4 config */ -#define GPIO_4_PORT GPIOF -#define GPIO_4_PIN 6 -#define GPIO_4_CLK 22 -#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PF) -#define GPIO_4_IRQ EXTI4_15_IRQn -/* GPIO channel 5 config */ -#define GPIO_5_PORT GPIOF -#define GPIO_5_PIN 7 -#define GPIO_5_CLK 22 -#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PF) -#define GPIO_5_IRQ EXTI4_15_IRQn -/* GPIO channel 6 config */ -#define GPIO_6_PORT GPIOC -#define GPIO_6_PIN 10 -#define GPIO_6_CLK 19 -#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PC) -#define GPIO_6_IRQ EXTI4_15_IRQn -/* GPIO channel 7 config */ -#define GPIO_7_PORT GPIOC -#define GPIO_7_PIN 11 -#define GPIO_7_CLK 19 -#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PC) -#define GPIO_7_IRQ EXTI4_15_IRQn -/* GPIO channel 8 config */ -#define GPIO_8_PORT GPIOC -#define GPIO_8_PIN 12 -#define GPIO_8_CLK 19 -#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PC) -#define GPIO_8_IRQ EXTI4_15_IRQn -/* GPIO channel 9 config */ -#define GPIO_9_PORT GPIOC -#define GPIO_9_PIN 13 -#define GPIO_9_CLK 19 -#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PC) -#define GPIO_9_IRQ EXTI4_15_IRQn -/* GPIO channel 10 config */ -#define GPIO_10_PORT GPIOC -#define GPIO_10_PIN 14 -#define GPIO_10_CLK 19 -#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI14_PC) -#define GPIO_10_IRQ EXTI4_15_IRQn -/* GPIO channel 11 config */ -#define GPIO_11_PORT GPIOC -#define GPIO_11_PIN 15 -#define GPIO_11_CLK 19 -#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI15_PC) -#define GPIO_11_IRQ EXTI4_15_IRQn -/** @} */ - #ifdef __cplusplus } #endif diff --git a/cpu/stm32f0/include/periph_cpu.h b/cpu/stm32f0/include/periph_cpu.h index d2a7560684..18b92485f6 100644 --- a/cpu/stm32f0/include/periph_cpu.h +++ b/cpu/stm32f0/include/periph_cpu.h @@ -20,12 +20,77 @@ #define PERIPH_CPU_H #include "periph_cpu_common.h" +#include "cpu.h" #ifdef __cplusplus extern "C" { #endif -/* to be filled */ +/** + * @brief Overwrite the default gpio_t type definition + * @{ + */ +#define HAVE_GPIO_T +typedef uint32_t gpio_t; +/** @} */ + +/** + * @brief Definition of a fitting UNDEF value + */ +#define GPIO_UNDEF (0xffffffff) + +/** + * @brief Define a CPU specific GPIO pin generator macro + */ +#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y) + +/** + * @brief Override flank configuration values + * @{ + */ +#define HAVE_GPIO_FLANK_T\ + +typedef enum { + GPIO_RISING = 1, /**< emit interrupt on rising flank */ + GPIO_FALLING = 2, /**< emit interrupt on falling flank */ + GPIO_BOTH = 3 /**< emit interrupt on both flanks */ +} gpio_flank_t; +/** @} */ + +/** + * @brief Available ports on the STM32F4 family + */ +enum { + PORT_A = 0, /**< port A */ + PORT_B = 1, /**< port B */ + PORT_C = 2, /**< port C */ + PORT_D = 3, /**< port D */ + PORT_F = 5, /**< port F */ +}; + +/** + * @brief Available MUX values for configuring a pin's alternate function + */ +typedef enum { + GPIO_AF0 = 0, /**< use alternate function 0 */ + GPIO_AF1, /**< use alternate function 1 */ + GPIO_AF2, /**< use alternate function 2 */ + GPIO_AF3, /**< use alternate function 3 */ + GPIO_AF4, /**< use alternate function 4 */ + GPIO_AF5, /**< use alternate function 5 */ + GPIO_AF6, /**< use alternate function 6 */ + GPIO_AF7, /**< use alternate function 7 */ +} gpio_af_t; + +/** + * @brief Configure the alternate function for the given pin + * + * @note This is meant for internal use in STM32F4 peripheral drivers only + * + * @param[in] pin pin to configure + * @param[in] af alternate function to use + */ +void gpio_init_af(gpio_t pin, gpio_af_t af); #ifdef __cplusplus } diff --git a/cpu/stm32f0/include/stm32f051x8.h b/cpu/stm32f0/include/stm32f051x8.h index 9be486842b..c769f28714 100644 --- a/cpu/stm32f0/include/stm32f051x8.h +++ b/cpu/stm32f0/include/stm32f051x8.h @@ -2,20 +2,20 @@ ****************************************************************************** * @file stm32f051x8.h * @author MCD Application Team - * @version V2.0.1 - * @date 18-June-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access * Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral?s registers hardware + * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,7 +46,7 @@ * @{ */ -/** @addtogroup cpu_specific_stm32f051x8 +/** @addtogroup stm32f051x8 * @{ */ @@ -60,7 +60,6 @@ /** @addtogroup Configuration_section_for_CMSIS * @{ */ - /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ @@ -73,7 +72,7 @@ * @} */ -/** @addtogroup cpu_specific_Peripheral_interrupt_number_definition +/** @addtogroup Peripheral_interrupt_number_definition * @{ */ @@ -128,7 +127,7 @@ typedef enum #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ #include -/** @addtogroup cpu_specific_Peripheral_registers_structures +/** @addtogroup Peripheral_registers_structures * @{ */ @@ -283,14 +282,12 @@ typedef struct */ typedef struct { - __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ - __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ - __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ - __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ - __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ - __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ - __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ - __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */ + __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ + __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ + __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ + __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ + __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ + __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ }OB_TypeDef; /** @@ -299,21 +296,16 @@ typedef struct typedef struct { - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - uint16_t RESERVED0; /*!< Reserved, 0x06 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - uint16_t RESERVED1; /*!< Reserved, 0x12 */ - __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - uint16_t RESERVED2; /*!< Reserved, 0x16 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ - __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ - uint16_t RESERVED3; /*!< Reserved, 0x2A */ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ }GPIO_TypeDef; /** @@ -373,6 +365,7 @@ typedef struct /** * @brief Reset and Clock Control */ + typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ @@ -394,7 +387,6 @@ typedef struct /** * @brief Real-Time Clock */ - typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ @@ -430,24 +422,15 @@ typedef struct typedef struct { - __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ }SPI_TypeDef; /** @@ -455,42 +438,27 @@ typedef struct */ typedef struct { - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ - uint16_t RESERVED10; /*!< Reserved, 0x2A */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED12; /*!< Reserved, 0x32 */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED17; /*!< Reserved, 0x26 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED18; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ - uint16_t RESERVED19; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED20; /*!< Reserved, 0x52 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ }TIM_TypeDef; /** @@ -523,19 +491,16 @@ typedef struct __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - uint16_t RESERVED1; /*!< Reserved, 0x0E */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ + uint16_t RESERVED1; /*!< Reserved, 0x26 */ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ + uint16_t RESERVED2; /*!< Reserved, 0x2A */ }USART_TypeDef; /** @@ -552,11 +517,12 @@ typedef struct * @} */ -/** @addtogroup cpu_specific_Peripheral_memory_map +/** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ @@ -578,6 +544,7 @@ typedef struct #define I2C2_BASE (APBPERIPH_BASE + 0x00005800) #define PWR_BASE (APBPERIPH_BASE + 0x00007000) #define DAC_BASE (APBPERIPH_BASE + 0x00007400) + #define CEC_BASE (APBPERIPH_BASE + 0x00007800) #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) @@ -616,7 +583,7 @@ typedef struct * @} */ -/** @addtogroup cpu_specific_Peripheral_declaration +/** @addtogroup Peripheral_declaration * @{ */ @@ -664,16 +631,15 @@ typedef struct #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) - /** * @} */ -/** @addtogroup cpu_specific_Exported_constants +/** @addtogroup Exported_constants * @{ */ - /** @addtogroup cpu_specific_Peripheral_Registers_Bits_Definition + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -804,7 +770,6 @@ typedef struct #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */ #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */ - /******************************************************************************/ /* */ /* HDMI-CEC (CEC) */ @@ -863,7 +828,6 @@ typedef struct #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */ #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */ - /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ @@ -911,24 +875,24 @@ typedef struct #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ /* COMPx bits definition */ -#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */ -#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */ -#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */ -#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */ -#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */ -#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */ -#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */ -#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */ -#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */ -#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */ -#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */ -#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */ -#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */ -#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */ -#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */ -#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ +#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ +#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ +#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ +#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ +#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ +#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ +#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ +#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */ +#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */ +#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */ +#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */ +#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */ +#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */ +#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */ +#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */ +#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */ /******************************************************************************/ /* */ @@ -951,7 +915,6 @@ typedef struct /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ - /******************************************************************************/ /* */ /* Digital to Analog Converter (DAC) */ @@ -972,16 +935,16 @@ typedef struct /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ -#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ -#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ -#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12RD register ******************/ #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ @@ -990,10 +953,10 @@ typedef struct #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8RD register ******************/ -#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ -#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ +#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */ /******************** Bit definition for DAC_SR register ********************/ #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ @@ -1288,8 +1251,8 @@ typedef struct #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ /****************** FLASH Keys **********************************************/ -#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ -#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 +#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */ #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */ @@ -1324,12 +1287,13 @@ typedef struct #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ -#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ +#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */ #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */ +#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */ /* Old BOOT1 bit definition, maintained for legacy purpose */ #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 @@ -2203,16 +2167,6 @@ typedef struct #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */ -/*!< USART2 Clock source selection */ -#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ -#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */ -#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */ -#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */ -#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */ - /******************* Bit definition for RCC_CR2 register *******************/ #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */ #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */ @@ -2492,91 +2446,91 @@ typedef struct /* */ /*****************************************************************************/ /******************* Bit definition for SPI_CR1 register *******************/ -#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ -#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ -#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ -#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ -#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ -#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ -#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ -#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ -#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ -#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ -#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ -#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ -#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */ -#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ -#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ +#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */ +#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */ +#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */ +#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */ +#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register *******************/ -#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */ -#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */ -#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */ -#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */ -#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */ -#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */ -#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */ -#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */ -#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */ -#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */ -#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */ -#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */ -#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */ +#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */ +#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */ +#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */ +#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */ +#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */ +#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */ /******************** Bit definition for SPI_SR register *******************/ -#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */ -#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */ -#define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */ -#define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */ -#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */ -#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */ -#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */ -#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */ -#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */ -#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */ -#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */ -#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */ -#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */ -#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */ -#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */ +#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */ +#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */ +#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */ +#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */ +#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */ +#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */ +#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */ +#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */ /******************** Bit definition for SPI_DR register *******************/ -#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ +#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register *****************/ -#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ +#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register *****************/ -#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ +#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register *****************/ -#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ +#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register ****************/ -#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,6 @@ /** @addtogroup Configuration_section_for_CMSIS * @{ */ - /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ @@ -452,6 +451,7 @@ typedef struct /** * @brief Reset and Clock Control */ + typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ @@ -473,7 +473,6 @@ typedef struct /** * @brief Real-Time Clock */ - typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ @@ -609,6 +608,7 @@ typedef struct */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ @@ -636,6 +636,7 @@ typedef struct #define CRS_BASE (APBPERIPH_BASE + 0x00006C00) #define PWR_BASE (APBPERIPH_BASE + 0x00007000) #define DAC_BASE (APBPERIPH_BASE + 0x00007400) + #define CEC_BASE (APBPERIPH_BASE + 0x00007800) #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) @@ -753,7 +754,6 @@ typedef struct #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) - /** * @} */ @@ -1129,9 +1129,10 @@ typedef struct /*! + * @author Hauke Petersen * * @} */ @@ -24,309 +24,100 @@ #include "periph/gpio.h" #include "periph_conf.h" -static gpio_isr_ctx_t gpio_config[GPIO_NUMOF]; +/** + * @brief The STM32F0 family has 16 external interrupt lines + */ +#define EXTI_NUMOF (16U) -/* static port mappings */ -static GPIO_TypeDef *const gpio_port_map[GPIO_NUMOF] = { -#if GPIO_0_EN - [GPIO_0] = GPIO_0_PORT, -#endif -#if GPIO_1_EN - [GPIO_1] = GPIO_1_PORT, -#endif -#if GPIO_2_EN - [GPIO_2] = GPIO_2_PORT, -#endif -#if GPIO_3_EN - [GPIO_3] = GPIO_3_PORT, -#endif -#if GPIO_4_EN - [GPIO_4] = GPIO_4_PORT, -#endif -#if GPIO_5_EN - [GPIO_5] = GPIO_5_PORT, -#endif -#if GPIO_6_EN - [GPIO_6] = GPIO_6_PORT, -#endif -#if GPIO_7_EN - [GPIO_7] = GPIO_7_PORT, -#endif -#if GPIO_8_EN - [GPIO_8] = GPIO_8_PORT, -#endif -#if GPIO_9_EN - [GPIO_9] = GPIO_9_PORT, -#endif -#if GPIO_10_EN - [GPIO_10] = GPIO_10_PORT, -#endif -#if GPIO_11_EN - [GPIO_11] = GPIO_11_PORT, -#endif -}; +/** + * @brief Allocate memory for one callback and argument per EXTI channel + */ +static gpio_isr_ctx_t gpio_config[EXTI_NUMOF]; -/* static pin mappings */ -static const uint8_t gpio_pin_map[GPIO_NUMOF] = { -#if GPIO_0_EN - [GPIO_0] = GPIO_0_PIN, -#endif -#if GPIO_1_EN - [GPIO_1] = GPIO_1_PIN, -#endif -#if GPIO_2_EN - [GPIO_2] = GPIO_2_PIN, -#endif -#if GPIO_3_EN - [GPIO_3] = GPIO_3_PIN, -#endif -#if GPIO_4_EN - [GPIO_4] = GPIO_4_PIN, -#endif -#if GPIO_5_EN - [GPIO_5] = GPIO_5_PIN, -#endif -#if GPIO_6_EN - [GPIO_6] = GPIO_6_PIN, -#endif -#if GPIO_7_EN - [GPIO_7] = GPIO_7_PIN, -#endif -#if GPIO_8_EN - [GPIO_8] = GPIO_8_PIN, -#endif -#if GPIO_9_EN - [GPIO_9] = GPIO_9_PIN, -#endif -#if GPIO_10_EN - [GPIO_10] = GPIO_10_PIN, -#endif -#if GPIO_11_EN - [GPIO_11] = GPIO_11_PIN, -#endif -}; - -/* static irq mappings */ -static const IRQn_Type gpio_irq_map[GPIO_NUMOF] = { -#if GPIO_0_EN - [GPIO_0] = GPIO_0_IRQ, -#endif -#if GPIO_1_EN - [GPIO_1] = GPIO_1_IRQ, -#endif -#if GPIO_2_EN - [GPIO_2] = GPIO_2_IRQ, -#endif -#if GPIO_3_EN - [GPIO_3] = GPIO_3_IRQ, -#endif -#if GPIO_4_EN - [GPIO_4] = GPIO_4_IRQ, -#endif -#if GPIO_5_EN - [GPIO_5] = GPIO_5_IRQ, -#endif -#if GPIO_6_EN - [GPIO_6] = GPIO_6_IRQ, -#endif -#if GPIO_7_EN - [GPIO_7] = GPIO_7_IRQ, -#endif -#if GPIO_8_EN - [GPIO_8] = GPIO_8_IRQ, -#endif -#if GPIO_9_EN - [GPIO_9] = GPIO_9_IRQ, -#endif -#if GPIO_10_EN - [GPIO_10] = GPIO_10_IRQ, -#endif -#if GPIO_11_EN - [GPIO_11] = GPIO_11_IRQ, -#endif -}; - -/* static clock mapping */ -static const uint8_t gpio_clock_map[GPIO_NUMOF] = { -#if GPIO_0_EN - [GPIO_0] = GPIO_0_CLK, -#endif -#if GPIO_1_EN - [GPIO_1] = GPIO_1_CLK, -#endif -#if GPIO_2_EN - [GPIO_2] = GPIO_2_CLK, -#endif -#if GPIO_3_EN - [GPIO_3] = GPIO_3_CLK, -#endif -#if GPIO_4_EN - [GPIO_4] = GPIO_4_CLK, -#endif -#if GPIO_5_EN - [GPIO_5] = GPIO_5_CLK, -#endif -#if GPIO_6_EN - [GPIO_6] = GPIO_6_CLK, -#endif -#if GPIO_7_EN - [GPIO_7] = GPIO_7_CLK, -#endif -#if GPIO_8_EN - [GPIO_8] = GPIO_8_CLK, -#endif -#if GPIO_9_EN - [GPIO_9] = GPIO_9_CLK, -#endif -#if GPIO_10_EN - [GPIO_10] = GPIO_10_CLK, -#endif -#if GPIO_11_EN - [GPIO_11] = GPIO_11_CLK, -#endif -}; - -int gpio_init(gpio_t dev, gpio_dir_t dir, gpio_pp_t pullup) +/** + * @brief Extract the port base address from the given pin identifier + */ +static inline GPIO_TypeDef *_port(gpio_t pin) { - GPIO_TypeDef *port; - uint8_t pin; - - if (dev >= GPIO_NUMOF) { - return -1; - } - - port = gpio_port_map[dev]; - pin = gpio_pin_map[dev]; - - RCC->AHBENR |= (1 << gpio_clock_map[dev]); - - port->PUPDR &= ~(3 << (2 * pin)); /* configure push-pull resistors */ - port->PUPDR |= (pullup << (2 * pin)); - - if (dir == GPIO_DIR_OUT) { - port->MODER &= ~(2 << (2 * pin)); /* set pin to output mode */ - port->MODER |= (1 << (2 * pin)); - port->OTYPER &= ~(1 << pin); /* set to push-pull configuration */ - port->OSPEEDR |= (3 << (2 * pin)); /* set to high speed */ - port->ODR &= ~(1 << pin); /* set pin to low signal */ - } - else { - port->MODER &= ~(3 << (2 * pin)); /* configure pin as input */ - - } - - return 0; /* all OK */ + return (GPIO_TypeDef *)(pin & ~(0x0f)); } -int gpio_init_int(gpio_t dev, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb, void *arg) +/** + * @brief Extract the port number form the given identifier + * + * The port number is extracted by looking at bits 10, 11, 12, 13 of the base + * register addresses. + */ +static inline int _port_num(gpio_t pin) { - int res; - uint8_t pin; + return ((pin >> 10) & 0x0f); +} - if (dev >= GPIO_NUMOF) { - return -1; +/** + * @brief Extract the pin number from the last 4 bit of the pin identifier + */ +static inline int _pin_num(gpio_t pin) +{ + return (pin & 0x0f); +} + +int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup) +{ + GPIO_TypeDef *port = _port(pin); + int pin_num = _pin_num(pin); + + /* enable clock */ + RCC->AHBENR |= (RCC_AHBENR_GPIOAEN << _port_num(pin)); + /* configure pull register */ + port->PUPDR &= ~(3 << (2 * pin_num)); + port->PUPDR |= (pullup << (2 * pin_num)); + /* set direction */ + if (dir == GPIO_DIR_OUT) { + port->MODER &= ~(3 << (2 * pin_num)); /* set pin to output mode */ + port->MODER |= (1 << (2 * pin_num)); + port->OTYPER &= ~(1 << pin_num); /* set to push-pull */ + port->OSPEEDR |= (3 << (2 * pin_num)); /* set to high speed */ + port->ODR &= ~(1 << pin_num); /* set pin to low signal */ } - - pin = gpio_pin_map[dev]; - - /* configure pin as input */ - res = gpio_init(dev, GPIO_DIR_IN, pullup); - if (res < 0) { - return res; + else { + port->MODER &= ~(3 << (2 * pin_num)); /* configure pin as input */ } + return 0; +} - /* set interrupt priority (its the same for all EXTI interrupts) */ - NVIC_SetPriority(EXTI0_1_IRQn, GPIO_IRQ_PRIO); - NVIC_SetPriority(EXTI2_3_IRQn, GPIO_IRQ_PRIO); - NVIC_SetPriority(EXTI4_15_IRQn, GPIO_IRQ_PRIO); +int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb, void *arg) +{ + int pin_num = _pin_num(pin); + int port_num = _port_num(pin); + + /* set callback */ + gpio_config[pin_num].cb = cb; + gpio_config[pin_num].arg = arg; /* enable clock of the SYSCFG module for EXTI configuration */ RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; - /* read pin number, set EXIT channel and enable global interrupt for EXTI channel */ - switch (dev) { -#ifdef GPIO_0_EN - case GPIO_0: - GPIO_0_EXTI_CFG(); - break; -#endif -#ifdef GPIO_1_EN - case GPIO_1: - GPIO_1_EXTI_CFG(); - break; -#endif -#ifdef GPIO_2_EN - case GPIO_2: - GPIO_2_EXTI_CFG(); - break; -#endif -#ifdef GPIO_3_EN - case GPIO_3: - GPIO_3_EXTI_CFG(); - break; -#endif -#ifdef GPIO_4_EN - case GPIO_4: - GPIO_4_EXTI_CFG(); - break; -#endif -#ifdef GPIO_5_EN - case GPIO_5: - GPIO_5_EXTI_CFG(); - break; -#endif -#ifdef GPIO_6_EN - case GPIO_6: - GPIO_6_EXTI_CFG(); - break; -#endif -#ifdef GPIO_7_EN - case GPIO_7: - GPIO_7_EXTI_CFG(); - break; -#endif -#ifdef GPIO_8_EN - case GPIO_8: - GPIO_8_EXTI_CFG(); - break; -#endif -#ifdef GPIO_9_EN - case GPIO_9: - GPIO_9_EXTI_CFG(); - break; -#endif -#ifdef GPIO_10_EN - case GPIO_10: - GPIO_10_EXTI_CFG(); - break; -#endif -#ifdef GPIO_11_EN - case GPIO_11: - GPIO_11_EXTI_CFG(); - break; -#endif - } - NVIC_EnableIRQ(gpio_irq_map[dev]); + /* initialize pin as input */ + gpio_init(pin, GPIO_DIR_IN, pullup); - /* set callback */ - gpio_config[dev].cb = cb; - gpio_config[dev].arg = arg; - - /* configure the event that triggers an interrupt */ - switch (flank) { - case GPIO_RISING: - EXTI->RTSR |= (1 << pin); - EXTI->FTSR &= ~(1 << pin); - break; - case GPIO_FALLING: - EXTI->RTSR &= ~(1 << pin); - EXTI->FTSR |= (1 << pin); - break; - case GPIO_BOTH: - EXTI->RTSR |= (1 << pin); - EXTI->FTSR |= (1 << pin); - break; + /* enable global pin interrupt */ + if (pin_num < 2) { + NVIC_EnableIRQ(EXTI2_3_IRQn + pin_num); } + else if (pin_num < 4) { + NVIC_EnableIRQ(EXTI2_3_IRQn); + } + else { + NVIC_EnableIRQ(EXTI4_15_IRQn); + } + /* configure the active flank */ + EXTI->RTSR &= ~(1 << pin_num); + EXTI->RTSR |= ((flank & 0x1) << pin_num); + EXTI->FTSR &= ~(1 << pin_num); + EXTI->FTSR |= ((flank >> 1) << pin_num); + /* enable specific pin as exti sources */ + SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4)); + SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4)); /* clear any pending requests */ EXTI->PR = (1 << pin); @@ -336,209 +127,77 @@ int gpio_init_int(gpio_t dev, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb return 0; } -void gpio_irq_enable(gpio_t dev) +void gpio_init_af(gpio_t pin, gpio_af_t af) { - uint8_t pin; + GPIO_TypeDef *port = _port(pin); + uint32_t pin_num = _pin_num(pin); - if (dev >= GPIO_NUMOF) { - return; - } - - pin = gpio_pin_map[dev]; - EXTI->IMR |= (1 << pin); + /* set pin to AF mode */ + port->MODER &= ~(3 << (2 * pin_num)); + port->MODER |= (2 << (2 * pin_num)); + /* set selected function */ + port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4)); + port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4)); } -void gpio_irq_disable(gpio_t dev) +void gpio_irq_enable(gpio_t pin) { - uint8_t pin; - - if (dev >= GPIO_NUMOF) { - return; - } - - pin = gpio_pin_map[dev]; - EXTI->IMR &= ~(1 << pin); + EXTI->IMR |= (1 << _pin_num(pin)); } -int gpio_read(gpio_t dev) +void gpio_irq_disable(gpio_t pin) { - GPIO_TypeDef *port; - uint8_t pin; + EXTI->IMR &= ~(1 << _pin_num(pin)); +} - if (dev >= GPIO_NUMOF) { - return -1; - } +int gpio_read(gpio_t pin) +{ + GPIO_TypeDef *port = _port(pin); + uint32_t pin_num = _pin_num(pin); - port = gpio_port_map[dev]; - pin = gpio_pin_map[dev]; - - if (port->MODER & (1 << (pin * 2))) { /* if configured as output */ - return port->ODR & (1 << pin); /* read output data register */ + if (port->MODER & (1 << (pin_num * 2))) { /* if configured as output */ + return port->ODR & (1 << pin_num); /* read output data reg */ } else { - return port->IDR & (1 << pin); /* else read input data register */ + return port->IDR & (1 << pin_num); /* else read input data reg */ } } -void gpio_set(gpio_t dev) +void gpio_set(gpio_t pin) { - GPIO_TypeDef *port; - uint8_t pin; - - if (dev >= GPIO_NUMOF) { - return; - } - - port = gpio_port_map[dev]; - pin = gpio_pin_map[dev]; - - port->ODR |= (1 << pin); + _port(pin)->BSRR = (1 << _pin_num(pin)); } -void gpio_clear(gpio_t dev) +void gpio_clear(gpio_t pin) { - GPIO_TypeDef *port; - uint8_t pin; - - if (dev >= GPIO_NUMOF) { - return; - } - - port = gpio_port_map[dev]; - pin = gpio_pin_map[dev]; - - port->ODR &= ~(1 << pin); + _port(pin)->BSRR = ((1 << _pin_num(pin)) << 16); } -void gpio_toggle(gpio_t dev) +void gpio_toggle(gpio_t pin) { - if (gpio_read(dev)) { - gpio_clear(dev); + if (gpio_read(pin)) { + _port(pin)->BSRR = ((1 << _pin_num(pin))<< 16); } else { - gpio_set(dev); + _port(pin)->BSRR = (1 << _pin_num(pin)); } } -void gpio_write(gpio_t dev, int value) +void gpio_write(gpio_t pin, int value) { if (value) { - gpio_set(dev); + _port(pin)->BSRR = (1 << _pin_num(pin)); } else { - gpio_clear(dev); + _port(pin)->BSRR = ((1 << _pin_num(pin)) << 16); } } -void isr_exti0_1(void) +void isr_exti(void) { -#if GPIO_IRQ_0 >= 0 - if (EXTI->PR & EXTI_PR_PR0) { - EXTI->PR |= EXTI_PR_PR0; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_0].cb(gpio_config[GPIO_IRQ_0].arg); + for (size_t i = 0; i < EXTI_NUMOF; i++) { + if (EXTI->PR & (1 << i)) { + EXTI->PR = (1 << i); /* clear by writing a 1 */ + gpio_config[i].cb(gpio_config[i].arg); + } } -#endif -#if GPIO_IRQ_1 >= 0 - if (EXTI->PR & EXTI_PR_PR1) { - EXTI->PR |= EXTI_PR_PR1; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_1].cb(gpio_config[GPIO_IRQ_1].arg); - } -#endif - if (sched_context_switch_request) { - thread_yield(); - } -} - -void isr_exti2_3(void) -{ -#if GPIO_IRQ_2 >= 0 - if (EXTI->PR & EXTI_PR_PR2) { - EXTI->PR |= EXTI_PR_PR2; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_2].cb(gpio_config[GPIO_IRQ_2].arg); - } -#endif -#if GPIO_IRQ_3 >= 0 - if (EXTI->PR & EXTI_PR_PR3) { - EXTI->PR |= EXTI_PR_PR3; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_3].cb(gpio_config[GPIO_IRQ_3].arg); - } -#endif - if (sched_context_switch_request) { - thread_yield(); - } -} - -void isr_exti4_15(void) -{ -#if GPIO_IRQ_4 >= 0 - if (EXTI->PR & EXTI_PR_PR4) { - EXTI->PR |= EXTI_PR_PR4; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_4].cb(gpio_config[GPIO_IRQ_4].arg); - } -#endif -#if GPIO_IRQ_5 >= 0 - if (EXTI->PR & EXTI_PR_PR5) { - EXTI->PR |= EXTI_PR_PR5; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_5].cb(gpio_config[GPIO_IRQ_5].arg); - } -#endif -#if GPIO_IRQ_6 >= 0 - if (EXTI->PR & EXTI_PR_PR6) { - EXTI->PR |= EXTI_PR_PR6; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_6].cb(gpio_config[GPIO_IRQ_6].arg); - } -#endif -#if GPIO_IRQ_7 >= 0 - if (EXTI->PR & EXTI_PR_PR7) { - EXTI->PR |= EXTI_PR_PR7; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_7].cb(gpio_config[GPIO_IRQ_7].arg); - } -#endif -#if GPIO_IRQ_8 >= 0 - if (EXTI->PR & EXTI_PR_PR8) { - EXTI->PR |= EXTI_PR_PR8; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_8].cb(gpio_config[GPIO_IRQ_8].arg); - } -#endif -#if GPIO_IRQ_9 >= 0 - if (EXTI->PR & EXTI_PR_PR9) { - EXTI->PR |= EXTI_PR_PR9; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_9].cb(gpio_config[GPIO_IRQ_9].arg); - } -#endif -#if GPIO_IRQ_10 >= 0 - if (EXTI->PR & EXTI_PR_PR10) { - EXTI->PR |= EXTI_PR_PR10; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_10].cb(gpio_config[GPIO_IRQ_10].arg); - } -#endif -#if GPIO_IRQ_11 >= 0 - if (EXTI->PR & EXTI_PR_PR11) { - EXTI->PR |= EXTI_PR_PR11; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_11].cb(gpio_config[GPIO_IRQ_11].arg); - } -#endif -#if GPIO_IRQ_12 >= 0 - if (EXTI->PR & EXTI_PR_PR12) { - EXTI->PR |= EXTI_PR_PR12; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_12].cb(gpio_config[GPIO_IRQ_12].arg); - } -#endif -#if GPIO_IRQ_13 >= 0 - if (EXTI->PR & EXTI_PR_PR13) { - EXTI->PR |= EXTI_PR_PR13; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_13].cb(gpio_config[GPIO_IRQ_13].arg); - } -#endif -#if GPIO_IRQ_14 >= 0 - if (EXTI->PR & EXTI_PR_PR14) { - EXTI->PR |= EXTI_PR_PR14; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_14].cb(gpio_config[GPIO_IRQ_14].arg); - } -#endif -#if GPIO_IRQ_15 >= 0 - if (EXTI->PR & EXTI_PR_PR15) { - EXTI->PR |= EXTI_PR_PR15; /* clear status bit by writing a 1 to it */ - gpio_config[GPIO_IRQ_15].cb(gpio_config[GPIO_IRQ_15].arg); - } -#endif if (sched_context_switch_request) { thread_yield(); } diff --git a/cpu/stm32f0/vectors.c b/cpu/stm32f0/vectors.c index 81e0503568..c368522d85 100644 --- a/cpu/stm32f0/vectors.c +++ b/cpu/stm32f0/vectors.c @@ -40,9 +40,7 @@ WEAK_DEFAULT void isr_pvd(void); WEAK_DEFAULT void isr_rtc(void); WEAK_DEFAULT void isr_flash(void); WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_exti0_1(void); -WEAK_DEFAULT void isr_exti2_3(void); -WEAK_DEFAULT void isr_exti4_15(void); +WEAK_DEFAULT void isr_exti(void); WEAK_DEFAULT void isr_ts(void); WEAK_DEFAULT void isr_dma1_ch1(void); WEAK_DEFAULT void isr_dma1_ch2_3(void); @@ -95,9 +93,9 @@ ISR_VECTORS const void *interrupt_vector[] = { (void*) isr_rtc, /* real time clock */ (void*) isr_flash, /* flash memory controller */ (void*) isr_rcc, /* reset and clock control */ - (void*) isr_exti0_1, /* external interrupt lines 0 and 1 */ - (void*) isr_exti2_3, /* external interrupt lines 2 and 3 */ - (void*) isr_exti4_15, /* external interrupt lines 4 to 15 */ + (void*) isr_exti, /* external interrupt lines 0 and 1 */ + (void*) isr_exti, /* external interrupt lines 2 and 3 */ + (void*) isr_exti, /* external interrupt lines 4 and 15 */ (void*) isr_ts, /* touch sensing input*/ (void*) isr_dma1_ch1, /* direct memory access controller 1, channel 1*/ (void*) isr_dma1_ch2_3, /* direct memory access controller 1, channel 2 and 3*/