diff --git a/cpu/stm32_common/periph/flashpage.c b/cpu/stm32_common/periph/flashpage.c
index 8e99c3c7dd..ba304dc26c 100644
--- a/cpu/stm32_common/periph/flashpage.c
+++ b/cpu/stm32_common/periph/flashpage.c
@@ -38,7 +38,6 @@
 #define CNTRL_REG              (FLASH->PECR)
 #define CNTRL_REG_LOCK         (FLASH_PECR_PELOCK)
 #define FLASH_CR_PER           (FLASH_PECR_ERASE | FLASH_PECR_PROG)
-#define FLASH_CR_PG            (FLASH_PECR_FPRG | FLASH_PECR_PROG)
 #define FLASHPAGE_DIV          (4U) /* write 4 bytes in one go */
 #else
 #if defined(CPU_FAM_STM32L4)
@@ -77,7 +76,8 @@ static void _erase_page(void *page_addr)
     uint32_t *dst = page_addr;
 #else
     uint16_t *dst = page_addr;
-
+#endif
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
     uint32_t hsi_state = (RCC->CR & RCC_CR_HSION);
     /* the internal RC oscillator (HSI) must be enabled */
     stmclk_enable_hsi();
@@ -98,7 +98,6 @@ static void _erase_page(void *page_addr)
     *dst = (uint32_t)0;
 #elif defined(CPU_FAM_STM32L4)
     DEBUG("[flashpage] erase: setting the page address\n");
-    CNTRL_REG |= FLASH_CR_PER;
     uint8_t pn;
 #if FLASHPAGE_NUMOF <= 256
     pn = (uint8_t)flashpage_page(dst);
@@ -131,8 +130,7 @@ static void _erase_page(void *page_addr)
     /* lock the flash module again */
     _lock();
 
-#if !(defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
-      defined(CPU_FAM_STM32L4))
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
     /* restore the HSI state */
     if (!hsi_state) {
         stmclk_disable_hsi();
@@ -163,7 +161,9 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
 #else
     uint16_t *dst = (uint16_t *)target_addr;
     const uint16_t *data_addr = data;
+#endif
 
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
     uint32_t hsi_state = (RCC->CR & RCC_CR_HSION);
     /* the internal RC oscillator (HSI) must be enabled */
     stmclk_enable_hsi();
@@ -173,7 +173,8 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
     _unlock_flash();
 
     DEBUG("[flashpage_raw] write: now writing the data\n");
-#if !(defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1))
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
+    defined(CPU_FAM_STM32L4)
     /* set PG bit and program page to flash */
     CNTRL_REG |= FLASH_CR_PG;
 #endif
@@ -185,14 +186,16 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
     }
 
     /* clear program bit again */
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
+    defined(CPU_FAM_STM32L4)
     CNTRL_REG &= ~(FLASH_CR_PG);
+#endif
     DEBUG("[flashpage_raw] write: done writing data\n");
 
     /* lock the flash module again */
     _lock();
 
-#if !(defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
-      defined(CPU_FAM_STM32L4))
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1)
     /* restore the HSI state */
     if (!hsi_state) {
         stmclk_disable_hsi();