From 5cea49808aaa45aa5204e11795ac8a9b1a74ea00 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 12:29:05 +0200 Subject: [PATCH 1/5] boards/stm32f1f3: introduce default shared clock configuration --- .../stm32/include/f1f3/cfg_clock_default.h | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 boards/common/stm32/include/f1f3/cfg_clock_default.h diff --git a/boards/common/stm32/include/f1f3/cfg_clock_default.h b/boards/common/stm32/include/f1f3/cfg_clock_default.h new file mode 100644 index 0000000000..b15a136b36 --- /dev/null +++ b/boards/common/stm32/include/f1f3/cfg_clock_default.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2015 TriaGnoSys GmbH + * 2017 Alexander Kurth, Sören Tempel, Tristan Bruns + * 2020 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Default clock configuration for STM32F1/F3 + * + * @author Víctor Ariño + * @author Sören Tempel + * @author Tristan Bruns + * @author Alexander Kurth + * @author Alexandre Abadie + * + */ + +#ifndef F1F3_CFG_CLOCK_DEFAULT_H +#define F1F3_CFG_CLOCK_DEFAULT_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock settings + * @{ + */ +/* give the target core clock (HCLK) frequency [in Hz], + * maximum: 72MHz */ +#define CLOCK_CORECLOCK MHZ(72) +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#ifndef CLOCK_HSE +#define CLOCK_HSE MHZ(8) +#endif +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#ifndef CLOCK_LSE +#define CLOCK_LSE (0) +#endif +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) + +/* PLL factors */ +#ifndef CLOCK_PLL_PREDIV +#define CLOCK_PLL_PREDIV (1) +#endif +#ifndef CLOCK_PLL_MUL +#define CLOCK_PLL_MUL (9) +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* F1F3_CFG_CLOCK_DEFAULT_H */ +/** @} */ From 1b8460d68fe47897afd57f1fe1511012bedcc2c8 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 12:30:13 +0200 Subject: [PATCH 2/5] boards/stm32f1: use shared default clock configuration --- boards/common/blxxxpill/Makefile.include | 1 + boards/common/blxxxpill/include/periph_conf.h | 33 +++---------------- boards/maple-mini/Makefile.include | 3 ++ boards/maple-mini/include/periph_conf.h | 30 +---------------- boards/nucleo-f103rb/include/periph_conf.h | 33 +++---------------- boards/olimexino-stm32/include/periph_conf.h | 33 +++---------------- boards/opencm904/Makefile.include | 3 ++ boards/opencm904/include/periph_conf.h | 30 +---------------- boards/spark-core/Makefile.include | 3 ++ boards/spark-core/include/periph_conf.h | 30 +---------------- 10 files changed, 25 insertions(+), 174 deletions(-) diff --git a/boards/common/blxxxpill/Makefile.include b/boards/common/blxxxpill/Makefile.include index ecbe5bfa91..139555db3f 100644 --- a/boards/common/blxxxpill/Makefile.include +++ b/boards/common/blxxxpill/Makefile.include @@ -1,3 +1,4 @@ +INCLUDES += -I$(RIOTBOARD)/common/stm32/include INCLUDES += -I$(RIOTBOARD)/common/blxxxpill/include ifeq (dfu-util,$(PROGRAMMER)) diff --git a/boards/common/blxxxpill/include/periph_conf.h b/boards/common/blxxxpill/include/periph_conf.h index 2e813b07eb..f6ad5a7799 100644 --- a/boards/common/blxxxpill/include/periph_conf.h +++ b/boards/common/blxxxpill/include/periph_conf.h @@ -24,41 +24,16 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* blxxxpill boards provide an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1U) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name Real time counter configuration * @{ diff --git a/boards/maple-mini/Makefile.include b/boards/maple-mini/Makefile.include index d39a097844..09912771ba 100644 --- a/boards/maple-mini/Makefile.include +++ b/boards/maple-mini/Makefile.include @@ -1,3 +1,6 @@ +# Include shared STM32 headers +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyACM0 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) diff --git a/boards/maple-mini/include/periph_conf.h b/boards/maple-mini/include/periph_conf.h index 60a8f05102..a278044de4 100644 --- a/boards/maple-mini/include/periph_conf.h +++ b/boards/maple-mini/include/periph_conf.h @@ -20,40 +20,12 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (0U) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/nucleo-f103rb/include/periph_conf.h b/boards/nucleo-f103rb/include/periph_conf.h index c34ff0ffe9..4205f526aa 100644 --- a/boards/nucleo-f103rb/include/periph_conf.h +++ b/boards/nucleo-f103rb/include/periph_conf.h @@ -19,41 +19,16 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/olimexino-stm32/include/periph_conf.h b/boards/olimexino-stm32/include/periph_conf.h index effbffbde8..1820912345 100644 --- a/boards/olimexino-stm32/include/periph_conf.h +++ b/boards/olimexino-stm32/include/periph_conf.h @@ -19,41 +19,16 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name ADC configuration * @{ diff --git a/boards/opencm904/Makefile.include b/boards/opencm904/Makefile.include index 702f620de9..9f534872e1 100644 --- a/boards/opencm904/Makefile.include +++ b/boards/opencm904/Makefile.include @@ -1,3 +1,6 @@ +# Include shared STM32 headers +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyACM0 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) diff --git a/boards/opencm904/include/periph_conf.h b/boards/opencm904/include/periph_conf.h index 72a9ef9942..d18121c9e6 100644 --- a/boards/opencm904/include/periph_conf.h +++ b/boards/opencm904/include/periph_conf.h @@ -20,40 +20,12 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (0U) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/spark-core/Makefile.include b/boards/spark-core/Makefile.include index 2554641f79..06c8e18cda 100644 --- a/boards/spark-core/Makefile.include +++ b/boards/spark-core/Makefile.include @@ -1,3 +1,6 @@ +# Include shared STM32 headers +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + # configure the serial interface PORT_LINUX ?= /dev/ttyUSB0 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) diff --git a/boards/spark-core/include/periph_conf.h b/boards/spark-core/include/periph_conf.h index 43ef4b8a1a..a60f56052e 100644 --- a/boards/spark-core/include/periph_conf.h +++ b/boards/spark-core/include/periph_conf.h @@ -20,40 +20,12 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif - /** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ - /* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ - #define CLOCK_CORECLOCK (72000000U) - /* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ - #define CLOCK_HSE (8000000U) - /* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ - #define CLOCK_LSE (0U) - /* peripheral clock setup */ - #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 - #define CLOCK_AHB (CLOCK_CORECLOCK / 1) - #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ - #define CLOCK_APB1 (CLOCK_CORECLOCK / 2) - #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ - #define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - - /* PLL factors */ - #define CLOCK_PLL_PREDIV (1) - #define CLOCK_PLL_MUL (9) - /** @} */ - /** * @name Timer configuration * @{ From 6a6084dfe78fada5baa264b011ce0132cf87f914 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 12:30:50 +0200 Subject: [PATCH 3/5] boards/nucleo-f3xx: use shared default clock configuration --- boards/nucleo-f302r8/include/periph_conf.h | 33 +++---------------- boards/nucleo-f303k8/include/periph_conf.h | 37 +++++----------------- boards/nucleo-f303re/include/periph_conf.h | 33 +++---------------- boards/nucleo-f303ze/include/periph_conf.h | 33 +++---------------- boards/nucleo-f334r8/include/periph_conf.h | 33 +++---------------- 5 files changed, 24 insertions(+), 145 deletions(-) diff --git a/boards/nucleo-f302r8/include/periph_conf.h b/boards/nucleo-f302r8/include/periph_conf.h index e13639a700..034fcde657 100644 --- a/boards/nucleo-f302r8/include/periph_conf.h +++ b/boards/nucleo-f302r8/include/periph_conf.h @@ -23,42 +23,17 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-f303k8/include/periph_conf.h b/boards/nucleo-f303k8/include/periph_conf.h index a3cdb158a0..cebd2e03a0 100644 --- a/boards/nucleo-f303k8/include/periph_conf.h +++ b/boards/nucleo-f303k8/include/periph_conf.h @@ -19,42 +19,21 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* No HSE available for this board */ +#define CLOCK_HSE (0U) + +/* Adjust PLL prescalers to reach 72MHz sysclock */ +#define CLOCK_PLL_PREDIV (2) +#define CLOCK_PLL_MUL (16) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (64000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (0) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (2) -#define CLOCK_PLL_MUL (16) -/** @} */ - /** * @name DMA streams configuration * @{ diff --git a/boards/nucleo-f303re/include/periph_conf.h b/boards/nucleo-f303re/include/periph_conf.h index 9df821b3da..f21a70f427 100644 --- a/boards/nucleo-f303re/include/periph_conf.h +++ b/boards/nucleo-f303re/include/periph_conf.h @@ -21,42 +21,17 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-f303ze/include/periph_conf.h b/boards/nucleo-f303ze/include/periph_conf.h index 9cb3ea391b..d3268c00a4 100644 --- a/boards/nucleo-f303ze/include/periph_conf.h +++ b/boards/nucleo-f303ze/include/periph_conf.h @@ -19,42 +19,17 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-f334r8/include/periph_conf.h b/boards/nucleo-f334r8/include/periph_conf.h index 52bbf92b86..d5d5bc1914 100644 --- a/boards/nucleo-f334r8/include/periph_conf.h +++ b/boards/nucleo-f334r8/include/periph_conf.h @@ -20,42 +20,17 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name DMA streams configuration * @{ From 9f129086447459ed504cf74f389547b24d6cb4be Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 12:47:55 +0200 Subject: [PATCH 4/5] boards/fox: iotlab: use shared default clock configuration --- boards/common/iotlab/Makefile.include | 1 + .../iotlab/include/periph_conf_common.h | 40 +++++-------------- boards/fox/Makefile.include | 3 ++ boards/fox/include/periph_conf.h | 39 +++++------------- 4 files changed, 24 insertions(+), 59 deletions(-) diff --git a/boards/common/iotlab/Makefile.include b/boards/common/iotlab/Makefile.include index 35cfb0996d..6f89fa3d85 100644 --- a/boards/common/iotlab/Makefile.include +++ b/boards/common/iotlab/Makefile.include @@ -17,4 +17,5 @@ OPENOCD_CONFIG ?= $(RIOTBOARD)/common/iotlab/dist/openocd.cfg include $(RIOTMAKE)/tools/openocd.inc.mk # add the common header files to the include path +INCLUDES += -I$(RIOTBOARD)/common/stm32/include INCLUDES += -I$(RIOTBOARD)/common/iotlab/include diff --git a/boards/common/iotlab/include/periph_conf_common.h b/boards/common/iotlab/include/periph_conf_common.h index 178a6e0853..0a0b6ebf1a 100644 --- a/boards/common/iotlab/include/periph_conf_common.h +++ b/boards/common/iotlab/include/periph_conf_common.h @@ -20,42 +20,22 @@ #ifndef PERIPH_CONF_COMMON_H #define PERIPH_CONF_COMMON_H +/* iotlab boards provide an LSE */ +#define CLOCK_LSE (1) + +/* HSE is clocked at 16MHz */ +#define CLOCK_HSE MHZ(16) + +/* Adjust PLL predevider to reach 72MHz sysclock */ +#define CLOCK_PLL_PREDIV (2) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif - -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ - #define CLOCK_CORECLOCK (72000000U) - /* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ - #define CLOCK_HSE (16000000U) - /* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ - #define CLOCK_LSE (1) - /* peripheral clock setup */ - #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 - #define CLOCK_AHB (CLOCK_CORECLOCK / 1) - #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ - #define CLOCK_APB1 (CLOCK_CORECLOCK / 2) - #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ - #define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - - /* PLL factors */ - #define CLOCK_PLL_PREDIV (2) - #define CLOCK_PLL_MUL (9) - /** @} */ - /** * @name ADC configuration * @{ diff --git a/boards/fox/Makefile.include b/boards/fox/Makefile.include index 8ebfabac89..59dcb087ce 100644 --- a/boards/fox/Makefile.include +++ b/boards/fox/Makefile.include @@ -1,3 +1,6 @@ +# Include shared STM32 headers +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + # set default port depending on operating system PORT_LINUX ?= /dev/ttyUSB1 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbserial*))) diff --git a/boards/fox/include/periph_conf.h b/boards/fox/include/periph_conf.h index 4ad37d8efd..c308261c31 100644 --- a/boards/fox/include/periph_conf.h +++ b/boards/fox/include/periph_conf.h @@ -19,41 +19,22 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* iotlab boards provide an LSE */ +#define CLOCK_LSE (1) + +/* HSE is clocked at 16MHz */ +#define CLOCK_HSE MHZ(16) + +/* Adjust PLL predevider to reach 72MHz sysclock */ +#define CLOCK_PLL_PREDIV (2) + #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (16000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1U) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (2) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name Timer configuration * @{ From f9a4dddc90668061cccd345edbdbf451ad96e7f8 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 22:17:23 +0200 Subject: [PATCH 5/5] boards/stm32f3disco: use shared default clock configuration --- boards/stm32f3discovery/Makefile.include | 3 ++ boards/stm32f3discovery/include/periph_conf.h | 30 +------------------ 2 files changed, 4 insertions(+), 29 deletions(-) diff --git a/boards/stm32f3discovery/Makefile.include b/boards/stm32f3discovery/Makefile.include index 2c9ac5007b..cf7a23963d 100644 --- a/boards/stm32f3discovery/Makefile.include +++ b/boards/stm32f3discovery/Makefile.include @@ -1,3 +1,6 @@ +# add the common header files to the include path +INCLUDES += -I$(RIOTBOARD)/common/stm32/include + # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyUSB0 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) diff --git a/boards/stm32f3discovery/include/periph_conf.h b/boards/stm32f3discovery/include/periph_conf.h index 54df0a1a52..1b6f6cb6aa 100644 --- a/boards/stm32f3discovery/include/periph_conf.h +++ b/boards/stm32f3discovery/include/periph_conf.h @@ -20,40 +20,12 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 72MHz */ -#define CLOCK_CORECLOCK (72000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (0) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 2) -#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */ -#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (9) -/** @} */ - /** * @name DAC configuration * @{