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cpu/lm4f120: adapted GPIO driver

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This commit is contained in:
Hauke Petersen 2016-02-29 17:37:10 +01:00
parent 0e4446e261
commit a7790625a1
2 changed files with 30 additions and 5 deletions
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15
cpu/lm4f120/include/periph_cpu.h
View File

@ -40,6 +40,21 @@ typedef uint32_t gpio_t;
#define GPIO_PIN(x,y) ((gpio_t)((x<<4) | y)) #define GPIO_PIN(x,y) ((gpio_t)((x<<4) | y))
/** @} */ /** @} */
/**
* @brief Override GPIO modes
* @{
*/
#define HAVE_GPIO_MODE_T
typedef enum {
GPIO_IN = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD << 4)), /**< IN */
GPIO_IN_PD = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPD << 4)), /**< IN with pull-down */
GPIO_IN_PU = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPU << 4)), /**< IN with pull-up */
GPIO_OUT = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_STD << 4)), /**< OUT (push-pull) */
GPIO_OD = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD << 4)), /**< OD */
GPIO_OD_PU = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD_WPU << 4)), /**< OD with pull-up */
} gpio_mode_t;
/** @} */
/** /**
* @brief Override values for pull register configuration * @brief Override values for pull register configuration
* @{ * @{

20
cpu/lm4f120/periph/gpio.c
View File

@ -29,6 +29,16 @@
#define ENABLE_DEBUG (0) #define ENABLE_DEBUG (0)
#include "debug.h" #include "debug.h"
/**
* @brief Mask out the pin type from the gpio_mode_t value
*/
#define TYPE(mode) (mode >> 4)
/**
* @brief Mask out the pin mode from the gpio_mode_t value
*/
#define MODE(mode) (mode & 0x0f)
/** /**
* @brief Extract the pin number of the given pin * @brief Extract the pin number of the given pin
*/ */
@ -90,7 +100,7 @@ static inline uint16_t _port_addr(gpio_t pin)
return port_addr; return port_addr;
} }
int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup) int gpio_init(gpio_t pin, gpio_mode_t mode)
{ {
const uint8_t port_num = _port_num(pin); const uint8_t port_num = _port_num(pin);
const uint32_t port_addr = _port_base[port_num]; const uint32_t port_addr = _port_base[port_num];
@ -109,8 +119,8 @@ int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup)
HWREG(port_addr+GPIO_LOCK_R_OFF) = 0; HWREG(port_addr+GPIO_LOCK_R_OFF) = 0;
ROM_GPIOPadConfigSet(port_addr, pin_bit, ROM_GPIOPadConfigSet(port_addr, pin_bit,
GPIO_STRENGTH_2MA, pullup); GPIO_STRENGTH_2MA, TYPE(mode));
ROM_GPIODirModeSet(port_addr, pin_bit, dir); ROM_GPIODirModeSet(port_addr, pin_bit, MODE(mode));
return 0; return 0;
} }
@ -156,7 +166,7 @@ void isr_gpio_portf(void){
_isr_gpio(5); _isr_gpio(5);
} }
int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank, int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg) gpio_cb_t cb, void *arg)
{ {
const uint8_t port_num = _port_num(pin); const uint8_t port_num = _port_num(pin);
@ -176,7 +186,7 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
ROM_GPIODirModeSet(port_addr, 1<<pin_num, GPIO_DIR_MODE_IN); ROM_GPIODirModeSet(port_addr, 1<<pin_num, GPIO_DIR_MODE_IN);
ROM_GPIOPadConfigSet(port_addr, 1<<pin_num, ROM_GPIOPadConfigSet(port_addr, 1<<pin_num,
GPIO_STRENGTH_2MA, pullup); GPIO_STRENGTH_2MA, TYPE(mode));
ROM_IntMasterDisable(); ROM_IntMasterDisable();