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cpu/esp32: fix typos

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This commit is contained in:
Kaspar Schleiser 2019-10-23 21:13:52 +02:00
parent 6b233780ae
commit a8c3c6ab68
20 changed files with 38 additions and 38 deletions
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18
cpu/esp32/doc.txt
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@ -73,8 +73,8 @@ The following table gives a short reference of all board configuration parameter
Parameter | Short Description | Type*
----------|----------------------------------------|------
[ADC_GPIOS](#esp32_adc_channels) | GPIOs that can be used as ADC channels | m
[CAN_TX](#esp32_can_interfaces) | GPIO used as CAN tranceiver TX signal | o
[CAN_RX](#esp32_can_interfaces) | GPIO used as CAN tranceiver RX signal | o
[CAN_TX](#esp32_can_interfaces) | GPIO used as CAN transceiver TX signal | o
[CAN_RX](#esp32_can_interfaces) | GPIO used as CAN transceiver RX signal | o
[DAC_GPIOS](#esp32_adc_channels) | GPIOs that can be used as DAC channels | m
[I2C0_SPEED](#esp32_i2c_interfaces)| Bus speed of I2C_DEV(0) | o
[I2C0_SCL](#esp32_i2c_interfaces) | GPIO used as SCL for I2C_DEV(0) | o
@ -877,11 +877,11 @@ in SJA1000 PeliCAN mode. Please refer the
[SJA1000 Datasheet](https://www.nxp.com/documents/data_sheet/SJA1000.pdf)
for detailed information about the CAN controller and its programming.
The pin configuration of the CAN tranceiver interface is usually defined
The pin configuration of the CAN transceiver interface is usually defined
in board specific peripheral configuration by
- <b>```CAN_TX```</b>, the GPIO used as TX tranceiver signal, and
- <b>```CAN_RX```</b>, the GPIO used as RX tranceiver signal.
- <b>```CAN_TX```</b>, the GPIO used as TX transceiver signal, and
- <b>```CAN_RX```</b>, the GPIO used as RX transceiver signal.
If the pin configuration is not defined, the following default configuration
is used which can be overridden by the application, see section
@ -894,8 +894,8 @@ CAN | RX | GPIO35 |`CAN_RX` | optional, can be overridden
Example:
```
#define CAN_TX GPIO10 /* CAN TX tranceiver signal */
#define CAN_RX GPIO9 /* CAN RX tranceiver signal */
#define CAN_TX GPIO10 /* CAN TX transceiver signal */
#define CAN_RX GPIO9 /* CAN RX transceiver signal */
```
If the board has an external transceiver module connected to the ESP32 on-board,
@ -1035,7 +1035,7 @@ USEMODULE += esp_now
For ESP-NOW, ESP32 nodes are used in WiFi SoftAP + Station mode to advertise their SSID and become visible to other ESP32 nodes. The SSID of an ESP32 node is the concatenation of the prefix ```RIOT_ESP_``` with the MAC address of its SoftAP WiFi interface. The driver periodically scans all visible ESP32 nodes.
The following parameters are defined for ESP-NOW nodes. These parameters can be overriden by [application-specific board configurations](#esp32_application_specific_board_configuration).
The following parameters are defined for ESP-NOW nodes. These parameters can be overridden by [application-specific board configurations](#esp32_application_specific_board_configuration).
<center>
@ -1173,7 +1173,7 @@ It is important to ensure that the application-specific driver parameter file ``
INCLUDES += -I$(APPDIR)
```
**Pleae note:** To make such application-specific board configurations dependent on the ESP32 MCU or a particular ESP32 board, you should always enclose these definitions in the following constructs:
**Please note:** To make such application-specific board configurations dependent on the ESP32 MCU or a particular ESP32 board, you should always enclose these definitions in the following constructs:
```
#ifdef CPU_ESP32
...

2
cpu/esp32/esp-eth/esp_eth_netdev.c
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@ -63,7 +63,7 @@
/**
* There is only one ESP-ETH device. We define it as static device variable
* to have accesss to the device inside ESP-ETH interrupt routines which do
* to have access to the device inside ESP-ETH interrupt routines which do
* not provide an argument that could be used as pointer to the ESP-ETH
* device which triggers the interrupt.
*/

4
cpu/esp32/esp-wifi/esp_wifi_netdev.c
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@ -69,7 +69,7 @@
/*
* There is only one ESP WiFi device. We define it as static device variable
* to have accesss to the device inside ESP WiFi interrupt routines which do
* to have access to the device inside ESP WiFi interrupt routines which do
* not provide an argument that could be used as pointer to the ESP WiFi
* device which triggers the interrupt.
*/
@ -79,7 +79,7 @@ static const netdev_driver_t _esp_wifi_driver;
/*
* Ring buffer for rx_buf elements which hold a pointer to the WiFi frame
* buffer, a pointer to the ethernet frame and the frame length for each
* received frame. Since we have anly one device, it the ring buffer can be
* received frame. Since we have only one device, it the ring buffer can be
* static and has not to be exposed as part of the network device.
*/
#ifndef ESP_WIFI_MAX_RX_BUF

2
cpu/esp32/freertos/queue.c
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@ -132,7 +132,7 @@ BaseType_t IRAM_ATTR _queue_generic_send(QueueHandle_t xQueue,
/* is there still space in the queue */
if (queue->item_level < queue->item_num || xCopyPosition == queueOVERWRITE) {
uint32_t write_pos;
/* determin the write position in the queue and update positions */
/* determine the write position in the queue and update positions */
if (xCopyPosition == queueSEND_TO_BACK) {
write_pos = queue->item_tail;
queue->item_tail = (queue->item_tail + 1) % queue->item_num;

2
cpu/esp32/include/can_params.h
View File

@ -34,7 +34,7 @@ extern "C" {
#endif
#ifndef CAN_RX
/** Default CAN tranceiver RX pin if not defined in board configuration */
/** Default CAN transceiver RX pin if not defined in board configuration */
#define CAN_RX GPIO35
#endif

2
cpu/esp32/include/esp_common.h
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@ -101,7 +101,7 @@ extern "C" {
#endif
/**
* @brief funcion name mappings for source code compatibility with ESP8266 port
* @brief function name mappings for source code compatibility with ESP8266 port
* @{
*/
#define system_get_cpu_freq ets_get_cpu_frequency

2
cpu/esp32/include/exceptions.h
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@ -24,7 +24,7 @@
extern "C" {
#endif
/** Initalize exception handler */
/** Initialize exception handler */
extern void init_exceptions(void);
#ifdef __cplusplus

6
cpu/esp32/include/gpio_arch.h
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@ -64,7 +64,7 @@ extern const uint32_t _gpio_to_iomux_reg[];
* @brief Set the usage type of the pin
* @param pin GPIO pin
* @param usage GPIO pin usage type
* @return 0 on succes
* @return 0 on success
* -1 on error
*/
int gpio_set_pin_usage(gpio_t pin, gpio_pin_usage_t usage);
@ -72,7 +72,7 @@ int gpio_set_pin_usage(gpio_t pin, gpio_pin_usage_t usage);
/**
* @brief Get the usage type of the pin
* @param pin GPIO pin
* @return GPIO pin usage type on succes
* @return GPIO pin usage type on success
* _NOT_EXIST on error
*/
gpio_pin_usage_t gpio_get_pin_usage(gpio_t pin);
@ -80,7 +80,7 @@ gpio_pin_usage_t gpio_get_pin_usage(gpio_t pin);
/**
* @brief Get the usage type of the pin as string
* @param pin GPIO pin
* @return GPIO pin usage type string on succes
* @return GPIO pin usage type string on success
* _NOT_EXIST on error
*/
const char* gpio_get_pin_usage_str(gpio_t pin);

8
cpu/esp32/include/sdk_conf.h
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@ -13,7 +13,7 @@
* @file
* @brief SDK configuration compatible to the ESP-IDF
*
* The SDK configuration can be partially overriden by application-specific
* The SDK configuration can be partially overridden by application-specific
* board configuration.
*
* @author Gunar Schorcht <gunar@schorcht.net>
@ -31,7 +31,7 @@ extern "C" {
#include "board.h"
/**
* @brief Defines the CPU frequency [vallues = 2, 40, 80, 160 and 240]
* @brief Defines the CPU frequency [values = 2, 40, 80, 160 and 240]
*/
#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
@ -41,7 +41,7 @@ extern "C" {
* Default console configuration
*
* STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and
* can be overriden by an application specific configuration.
* can be overridden by an application specific configuration.
*/
#define CONFIG_CONSOLE_UART_NUM 0
@ -59,7 +59,7 @@ extern "C" {
/**
* ESP32 specific configuration
*
* CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ can be overriden by an application
* CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ can be overridden by an application
* specific SDK configuration file.
*/
#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ

2
cpu/esp32/include/syscalls.h
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@ -47,7 +47,7 @@ uint64_t system_get_time_64 (void);
/** Time since boot in ms (32bit version) */
uint32_t system_get_time_ms (void);
/** initialize system watchdog timer ans start it */
/** initialize system watchdog timer and start it */
void system_wdt_init (void);
/** start the initialized system watchdog timer */

4
cpu/esp32/periph/adc_ctrl.c
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@ -110,7 +110,7 @@ static bool _adc2_ctrl_initialized = false;
void _adc1_ctrl_init(void)
{
/* return if already intialized */
/* return if already initialized */
if (_adc1_ctrl_initialized) {
return;
}
@ -149,7 +149,7 @@ void _adc1_ctrl_init(void)
void _adc2_ctrl_init(void)
{
/* return if already intialized */
/* return if already initialized */
if (_adc2_ctrl_initialized) {
return;
}

2
cpu/esp32/periph/can.c
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@ -251,7 +251,7 @@ static int _esp_can_send(candev_t *candev, const struct can_frame *frame)
/* save reference to frame in transmission (marks transmitter as busy) */
dev->tx_frame = (struct can_frame*)frame;
/* prepare the frame as exected by ESP32 */
/* prepare the frame as expected by ESP32 */
_esp_can_frame_t esp_frame = {};
esp_frame.dlc = frame->can_dlc;

2
cpu/esp32/periph/dac.c
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@ -61,7 +61,7 @@ int8_t dac_init (dac_t line)
uint8_t rtcio = _gpio_rtcio_map[dac_channels[line]];
uint8_t idx;
/* try to initialize the pin as DAC ouput */
/* try to initialize the pin as DAC output */
if (gpio_get_pin_usage(_adc_hw[rtcio].gpio) != _GPIO) {
LOG_TAG_ERROR("dac", "GPIO%d is used for %s and cannot be used as "
"DAC output\n", _adc_hw[rtcio].gpio,

4
cpu/esp32/periph/gpio.c
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@ -189,7 +189,7 @@ gpio_pin_usage_t _gpio_pin_usage [GPIO_PIN_NUMOF] = {
_SPIF, /* gpio7 not configurable, used as SPI MISO */
_SPIF, /* gpio8 not configurable, used as SPI MOSI */
#if defined(FLASH_MODE_QIO) || defined(FLASH_MODE_QOUT)
/* in qio and qout mode thes pins are used for quad SPI */
/* in qio and qout mode these pins are used for quad SPI */
_SPIF, /* gpio9 not configurable, used as SPI HD */
_SPIF, /* gpio10 not configurable, used as SPI WP */
#else
@ -274,7 +274,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
case GPIO_IN_PD:
case GPIO_IN_PU:
/* GPIOs 34 ... 39 have no software controlable pullups/pulldowns */
/* GPIOs 34 ... 39 have no software controllable pullups/pulldowns */
LOG_TAG_ERROR("gpio",
"GPIO%d has no pullups/pulldowns\n", pin);
return -1;

2
cpu/esp32/periph/i2c_hw.c
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@ -685,7 +685,7 @@ void _i2c_transfer_timeout (void *arg)
{
i2c_t dev = (i2c_t)arg;
/* reset the hardware if it I2C got stucked */
/* reset the hardware if it I2C got stuck */
_i2c_reset_hw(dev);
/* set result to timeout */

2
cpu/esp32/periph/i2c_sw.c
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@ -220,7 +220,7 @@ int /* IRAM */ i2c_read_bytes(i2c_t dev, uint16_t addr, void *data, size_t len,
/* prepare 10 bit address bytes */
uint8_t addr1 = 0xf0 | (addr & 0x0300) >> 7 | I2C_READ;
uint8_t addr2 = addr & 0xff;
/* send address bytes wit read flag */
/* send address bytes with read flag */
if ((res = _i2c_write_byte (bus, addr1)) != 0 ||
(res = _i2c_write_byte (bus, addr2)) != 0) {
/* abort transfer */

2
cpu/esp32/periph/timer.c
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@ -79,7 +79,7 @@ struct hw_timer_regs_t {
uint32_t unused : 10;
uint32_t ALARM_EN : 1; /* alarms are enabled */
uint32_t LEVEL_INT_EN: 1; /* alarms will generate level type interrupt */
uint32_t EDGE_INT_EN : 1; /* alarms will generate egde type interrupt */
uint32_t EDGE_INT_EN : 1; /* alarms will generate edge type interrupt */
uint32_t DIVIDER : 16; /* timer clock prescale value (basis is ABP) */
uint32_t AUTORELOAD : 1; /* auto-reload on alarms */
uint32_t INCREASE : 1; /* count up */

4
cpu/esp32/periph/uart.c
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@ -62,7 +62,7 @@ struct uart_hw_t {
uint8_t int_src; /* peripheral interrupt source used by the UART device */
};
/* hardware ressources */
/* hardware resources */
static struct uart_hw_t _uarts[] = {
{
.regs = &UART0,
@ -259,7 +259,7 @@ static uint8_t IRAM _uart_rx_one_char (uart_t uart)
/* send one data byte with wait */
static void _uart_tx_one_char(uart_t uart, uint8_t data)
{
/* wait until at least one byte is avaiable in the TX FIFO */
/* wait until at least one byte is available in the TX FIFO */
while (_uarts[uart].regs->status.txfifo_cnt >= UART_FIFO_MAX) {}
/* send the byte by placing it in the TX FIFO using MPU */

4
cpu/esp32/startup.c
View File

@ -216,7 +216,7 @@ static void IRAM system_clk_init (void)
/* determine configured CPU clock frequency from sdk_conf.h */
rtc_cpu_freq_t freq;
switch (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) {
case 40: freq = RTC_CPU_FREQ_XTAL; /* derived from external cristal */
case 40: freq = RTC_CPU_FREQ_XTAL; /* derived from external crystal */
break; /* normally 40 MHz */
case 80: freq = RTC_CPU_FREQ_80M; /* derived from PLL */
break;
@ -266,7 +266,7 @@ static NORETURN void IRAM system_init (void)
/* initialize the RTC module (restore timer values from RTC RAM) */
rtc_init();
/* install execption handlers */
/* install exception handlers */
init_exceptions();
/* clear interrupt matrix */

2
cpu/esp32/syscalls.c
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@ -241,7 +241,7 @@ void heap_stats(void)
#else /* MODULE_ESP_IDF_HEAP */
/* for compatibiliy with ESP-IDF heap functions */
/* for compatibility with ESP-IDF heap functions */
void* IRAM heap_caps_malloc( size_t size, uint32_t caps )
{
(void)caps;