diff --git a/cpu/stm32_common/include/periph_cpu_common.h b/cpu/stm32_common/include/periph_cpu_common.h index 367c03c426..94e85f7412 100644 --- a/cpu/stm32_common/include/periph_cpu_common.h +++ b/cpu/stm32_common/include/periph_cpu_common.h @@ -186,6 +186,14 @@ typedef struct { uint8_t dma_stream; /**< DMA stream used for TX */ uint8_t dma_chan; /**< DMA channel used for TX */ #endif +#ifdef UART_USE_HW_FC + gpio_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using HW flow control */ + gpio_t rts_pin; /**< RTS pin */ +#ifndef CPU_FAM_STM32F1 + gpio_af_t cts_af; /**< alternate function for CTS pin */ + gpio_af_t rts_af; /**< alternate function for RTS pin */ +#endif +#endif } uart_conf_t; /** diff --git a/cpu/stm32_common/periph/uart.c b/cpu/stm32_common/periph/uart.c index 7444cb3156..ee48f840b7 100644 --- a/cpu/stm32_common/periph/uart.c +++ b/cpu/stm32_common/periph/uart.c @@ -72,6 +72,18 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) gpio_init_af(uart_config[uart].rx_pin, uart_config[uart].rx_af); #endif } +#ifdef UART_USE_HW_FC + if (uart_config[uart].cts_pin != GPIO_UNDEF) { + gpio_init(uart_config[uart].cts_pin, GPIO_IN); + gpio_init(uart_config[uart].rts_pin, GPIO_OUT); +#ifdef CPU_FAM_STM32F1 + gpio_init_af(uart_config[uart].rts_pin, GPIO_AF_OUT_PP); +#else + gpio_init_af(uart_config[uart].cts_pin, uart_config[uart].cts_af); + gpio_init_af(uart_config[uart].rts_pin, uart_config[uart].rts_af); +#endif + } +#endif /* enable the clock */ periph_clk_en(uart_config[uart].bus, uart_config[uart].rcc_mask); @@ -96,6 +108,13 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) dev(uart)->CR1 = (USART_CR1_UE | USART_CR1_TE); } +#ifdef UART_USE_HW_FC + if (uart_config[uart].cts_pin != GPIO_UNDEF) { + /* configure hardware flow control */ + dev(uart)->CR3 = (USART_CR3_RTSE | USART_CR3_CTSE); + } +#endif + return UART_OK; }