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cpu/nrf51822: adapted to centralized cpu conf

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This commit is contained in:
Hauke Petersen 2015-05-27 23:06:34 +02:00
parent aa728e0506
commit a97cdaaf8d
3 changed files with 8 additions and 34 deletions
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5
cpu/nrf51822/cpu.c
View File

@ -25,9 +25,8 @@
*/
void cpu_init(void)
{
/* set pendSV interrupt to lowest possible priority */
NVIC_SetPriority(PendSV_IRQn, 0xff);
/* initialize the Cortex-M core */
cortexm_init();
/* set the correct clock source for HFCLK */
#if CLOCK_CRYSTAL == 32
NRF_CLOCK->XTALFREQ = CLOCK_XTALFREQ_XTALFREQ_32MHz;

31
cpu/nrf51822/include/cpu_conf.h
View File

@ -27,27 +27,11 @@ extern "C" {
#endif
/**
* @name Kernel configuration
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define THREAD_EXTRA_STACKSIZE_PRINTF (512)
#ifndef THREAD_STACKSIZE_DEFAULT
#define THREAD_STACKSIZE_DEFAULT (1024)
#endif
#define THREAD_STACKSIZE_IDLE (256)
/** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*
* TODO: remove once the remodeling of the uart0 driver is done
* @{
*/
#ifndef UART0_BUFSIZE
#define UART0_BUFSIZE (128)
#endif
#define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF (26U)
/** @} */
/**
@ -55,15 +39,6 @@ extern "C" {
*/
#define CPUID_ID_LEN (8)
/**
* @brief Definition of different panic modes
*/
typedef enum {
HARD_FAULT, /**< hard fault */
NMI_HANDLER, /**< non maskable interrupt */
DUMMY_HANDLER /**< dummy interrupt handler */
} panic_t;
#ifdef __cplusplus
}
#endif

6
cpu/nrf51822/startup.c
View File

@ -88,17 +88,17 @@ void reset_handler(void)
*/
void dummy_handler(void)
{
core_panic(DUMMY_HANDLER, "DUMMY ISR HANDLER");
core_panic(PANIC_DUMMY_HANDLER, "DUMMY ISR HANDLER");
}
void isr_nmi(void)
{
core_panic(NMI_HANDLER, "NMI HANDLER");
core_panic(PANIC_NMI_HANDLER, "NMI HANDLER");
}
void isr_hard_fault(void)
{
core_panic(HARD_FAULT, "HARD FAULT");
core_panic(PANIC_HARD_FAULT, "HARD FAULT");
}
/* Cortex-M specific interrupt vectors */