boards/nucleo-l496zg: add initial support
This commit is contained in:
Alexandre Abadie
parent
601846c2ba
commit
ac00b81e24
@ -60,7 +60,8 @@ extern "C" {
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#define ARDUINO_PIN_A0 GPIO_PIN(PORT_A, 3)
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#define ARDUINO_PIN_A1 GPIO_PIN(PORT_C, 0)
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#define ARDUINO_PIN_A2 GPIO_PIN(PORT_C, 3)
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#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F412ZG)
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#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F412ZG) || \
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defined(CPU_MODEL_STM32L496ZG)
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#define ARDUINO_PIN_A3 GPIO_PIN(PORT_C, 1)
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#define ARDUINO_PIN_A4 GPIO_PIN(PORT_C, 4)
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#define ARDUINO_PIN_A5 GPIO_PIN(PORT_C, 5)
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@ -37,11 +37,18 @@ extern "C" {
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* @name LED pin definitions and handlers
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* @{
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*/
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#if defined(CPU_MODEL_STM32L496ZG)
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#define LED0_PORT GPIOC
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#define LED0_PIN GPIO_PIN(PORT_C, 7)
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#define LED0_MASK (1 << 7)
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#else
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#define LED0_PORT GPIOB
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#define LED0_PIN GPIO_PIN(PORT_B, 0)
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#define LED0_MASK (1 << 0)
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#define LED0_ON (GPIOB->BSRR = LED0_MASK)
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#define LED0_OFF (GPIOB->BSRR = (LED0_MASK << 16))
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#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
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#endif
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#define LED0_ON (LED0_PORT->BSRR = LED0_MASK)
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#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 16))
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#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
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#define LED1_PIN GPIO_PIN(PORT_B, 7)
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#define LED1_MASK (1 << 7)
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4
boards/nucleo-l496zg/Makefile
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4
boards/nucleo-l496zg/Makefile
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@ -0,0 +1,4 @@
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MODULE = board
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DIRS = $(RIOTBOARD)/common/nucleo
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include $(RIOTBASE)/Makefile.base
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1
boards/nucleo-l496zg/Makefile.dep
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1
boards/nucleo-l496zg/Makefile.dep
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@ -0,0 +1 @@
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include $(RIOTBOARD)/common/nucleo/Makefile.dep
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16
boards/nucleo-l496zg/Makefile.features
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16
boards/nucleo-l496zg/Makefile.features
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@ -0,0 +1,16 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# load the common Makefile.features for Nucleo boards
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include $(RIOTBOARD)/common/nucleo144/Makefile.features
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m4_3
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-include $(RIOTCPU)/stm32l4/Makefile.features
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11
boards/nucleo-l496zg/Makefile.include
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11
boards/nucleo-l496zg/Makefile.include
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@ -0,0 +1,11 @@
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## the cpu to build for
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export CPU = stm32l4
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export CPU_MODEL = stm32l496zg
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# stdio is not available over st-link but on the Arduino TX/RX pins
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# A serial to USB converter plugged to the host is required
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PORT_LINUX ?= /dev/ttyUSB0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/common/nucleo144/Makefile.include
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5
boards/nucleo-l496zg/doc.txt
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5
boards/nucleo-l496zg/doc.txt
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@ -0,0 +1,5 @@
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/**
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* @defgroup boards_nucleo-l496zg STM32 Nucleo-L496ZG
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* @ingroup boards_common_nucleo144
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* @brief Support for the STM32 Nucleo-l496zg
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*/
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237
boards/nucleo-l496zg/include/periph_conf.h
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237
boards/nucleo-l496zg/include/periph_conf.h
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@ -0,0 +1,237 @@
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/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-l496zg
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo144-l496 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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#ifndef CLOCK_LSE
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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#endif
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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#ifndef CLOCK_MSI_LSE_PLL
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
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* Same as with CLOCK_LSE above this defaults to 0 because LSE is
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* mandatory for MSI/LSE-trimming to work */
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#define CLOCK_MSI_LSE_PLL (0)
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#endif
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
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#define CLOCK_CORECLOCK (80000000U)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI @ 48MHz
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [8:86]
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* R: post-divider, allowed range: [2,4,6,8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 80MHz MAX!
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*/
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (20)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR1_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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},
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR1_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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},
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim5
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR1_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 5,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_usart3)
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#define UART_0_DMA_ISR (isr_dma1_stream5)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM1,
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.rcc_mask = RCC_APB2ENR_TIM1EN,
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.chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
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{ .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
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{ .pin = GPIO_UNDEF, .cc_chan = 0} },
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.af = GPIO_AF1,
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.bus = APB2
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},
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{
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.dev = TIM4,
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.rcc_mask = RCC_APB1ENR1_TIM4EN,
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.chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
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{ .pin = GPIO_UNDEF, .cc_chan = 0},
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{ .pin = GPIO_UNDEF, .cc_chan = 0},
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{ .pin = GPIO_UNDEF, .cc_chan = 0} },
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.af = GPIO_AF2,
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.bus = APB1
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},
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 20000000Hz */
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7, /* -> 78125Hz */
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5, /* -> 312500Hz */
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3, /* -> 1250000Hz */
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1, /* -> 5000000Hz */
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0 /* -> 10000000Hz */
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},
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{ /* for APB2 @ 40000000Hz */
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7, /* -> 156250Hz */
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6, /* -> 312500Hz */
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4, /* -> 1250000Hz */
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2, /* -> 5000000Hz */
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1 /* -> 10000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (0)
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/** @} */
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/**
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* @name RTT configuration
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*
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* On the STM32Lx platforms, we always utilize the LPTIM1.
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* @{
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*/
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#define RTT_NUMOF (1)
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#define RTT_FREQUENCY (1024U) /* 32768 / 2^n */
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#define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
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/** @} */
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/**
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* @name RTC configuration
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* @{
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*/
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#define RTC_NUMOF (1)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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