riot-ci/RIOT
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

cpu/stm32_common: enable/disable uart peripheral

Browse Source 
in uart_poweroff the peripheral should be disabled through the register
instead of just disabling the peripheral clock. In uart_poweron the
peripheral should be enabled after enabling the clock.

Not explicitely disabling the peripheral causes some bad signals on the
uart line sometimes.
This commit is contained in:
Toon Stegen 2019-08-26 12:19:17 +02:00
parent 5ece3dc323
commit ac1d1ffda2
1 changed files with 44 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
cpu/stm32_common/periph/uart.c
View File

@ -107,6 +107,42 @@ static inline void uart_init_pins(uart_t uart, uart_rx_cb_t rx_cb)
#endif #endif
} }
static inline void uart_enable_clock(uart_t uart)
{
#ifdef STM32_PM_STOP
if (isr_ctx[uart].rx_cb) {
pm_block(STM32_PM_STOP);
}
#endif
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
if (uart_config[uart].cts_pin != GPIO_UNDEF) {
gpio_init(uart_config[uart].rts_pin, GPIO_OUT);
#ifdef CPU_FAM_STM32F1
gpio_init_af(uart_config[uart].rts_pin, GPIO_AF_OUT_PP);
#else
gpio_init_af(uart_config[uart].rts_pin, uart_config[uart].rts_af);
#endif
}
#endif
periph_clk_en(uart_config[uart].bus, uart_config[uart].rcc_mask);
}
static inline void uart_disable_clock(uart_t uart)
{
periph_clk_dis(uart_config[uart].bus, uart_config[uart].rcc_mask);
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
if (uart_config[uart].cts_pin != GPIO_UNDEF) {
gpio_init(uart_config[uart].rts_pin, GPIO_OUT);
gpio_set(uart_config[uart].rts_pin);
}
#endif
#ifdef STM32_PM_STOP
if (isr_ctx[uart].rx_cb) {
pm_unblock(STM32_PM_STOP);
}
#endif
}
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{ {
assert(uart < UART_NUMOF); assert(uart < UART_NUMOF);
@ -118,8 +154,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
uart_init_pins(uart, rx_cb); uart_init_pins(uart, rx_cb);
/* enable the clock */ uart_enable_clock(uart);
uart_poweron(uart);
/* reset UART configuration -> defaults to 8N1 mode */ /* reset UART configuration -> defaults to 8N1 mode */
dev(uart)->CR1 = 0; dev(uart)->CR1 = 0;
@ -330,40 +365,19 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
void uart_poweron(uart_t uart) void uart_poweron(uart_t uart)
{ {
assert(uart < UART_NUMOF); assert(uart < UART_NUMOF);
#ifdef STM32_PM_STOP
if (isr_ctx[uart].rx_cb) { uart_enable_clock(uart);
pm_block(STM32_PM_STOP);
} dev(uart)->CR1 |= (USART_CR1_UE);
#endif
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
if (uart_config[uart].cts_pin != GPIO_UNDEF) {
gpio_init(uart_config[uart].rts_pin, GPIO_OUT);
#ifdef CPU_FAM_STM32F1
gpio_init_af(uart_config[uart].rts_pin, GPIO_AF_OUT_PP);
#else
gpio_init_af(uart_config[uart].rts_pin, uart_config[uart].rts_af);
#endif
}
#endif
periph_clk_en(uart_config[uart].bus, uart_config[uart].rcc_mask);
} }
void uart_poweroff(uart_t uart) void uart_poweroff(uart_t uart)
{ {
assert(uart < UART_NUMOF); assert(uart < UART_NUMOF);
periph_clk_dis(uart_config[uart].bus, uart_config[uart].rcc_mask); dev(uart)->CR1 &= ~(USART_CR1_UE);
#ifdef MODULE_STM32_PERIPH_UART_HW_FC
if (uart_config[uart].cts_pin != GPIO_UNDEF) { uart_disable_clock(uart);
gpio_init(uart_config[uart].rts_pin, GPIO_OUT);
gpio_set(uart_config[uart].rts_pin);
}
#endif
#ifdef STM32_PM_STOP
if (isr_ctx[uart].rx_cb) {
pm_unblock(STM32_PM_STOP);
}
#endif
} }
static inline void irq_handler(uart_t uart) static inline void irq_handler(uart_t uart)