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Merge pull request #15117 from chrysn-pull-requests/nrf52-pwm-fixes

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cpu/nrf52: PWM fixes
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benpicco 2020-09-30 15:51:16 +02:00 committed by GitHub
commit add0814cd0
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3 changed files with 11 additions and 5 deletions
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4
cpu/nrf52/include/periph_cpu.h
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@ -173,6 +173,10 @@ typedef enum {
* @note define unused pins only from right to left, so the defined channels * @note define unused pins only from right to left, so the defined channels
* always start with channel 0 to x and the undefined ones are from x+1 * always start with channel 0 to x and the undefined ones are from x+1
* to PWM_CHANNELS. * to PWM_CHANNELS.
*
* @warning All the channels not in active use must be set to GPIO_UNDEF; just
* initializing fewer members of pin would insert a 0 value, which
* would be interpreted as the P0.00 pin that's then driven.
*/ */
#if defined(PWM_PRESENT) || DOXYGEN #if defined(PWM_PRESENT) || DOXYGEN
typedef struct { typedef struct {

10
cpu/nrf52/periph/pwm.c
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@ -90,12 +90,12 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
/* pin configuration */ /* pin configuration */
for (unsigned i = 0; i < PWM_CHANNELS; i++) { for (unsigned i = 0; i < PWM_CHANNELS; i++) {
if (pwm_config[pwm].pin[i] != GPIO_UNDEF) {
NRF_P0->PIN_CNF[pwm_config[pwm].pin[i]] = PIN_CNF_SET;
}
/* either left aligned pol or inverted duty cycle */ /* either left aligned pol or inverted duty cycle */
pwm_seq[pwm][i] = (POL_MASK & mode) ? POL_MASK : res; pwm_seq[pwm][i] = (POL_MASK & mode) ? POL_MASK : res;
dev(pwm)->PSEL.OUT[i] = pwm_config[pwm].pin[i]; /* Sign-extend the undefined pin into a value that also sets the
* 'Disconnected' field, and is also that register's reset state */
uint32_t extended_pin = (int32_t)(int8_t)pwm_config[pwm].pin[i];
dev(pwm)->PSEL.OUT[i] = extended_pin;
DEBUG("set PIN[%i] to %i with 0x%x\n", DEBUG("set PIN[%i] to %i with 0x%x\n",
(int)i, (int)pwm_config[pwm].pin[i], pwm_seq[pwm][i]); (int)i, (int)pwm_config[pwm].pin[i], pwm_seq[pwm][i]);
} }
@ -118,7 +118,7 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
/* setup the sequence */ /* setup the sequence */
dev(pwm)->SEQ[0].PTR = (uint32_t)pwm_seq[pwm]; dev(pwm)->SEQ[0].PTR = (uint32_t)pwm_seq[pwm];
dev(pwm)->SEQ[0].CNT = pwm_channels(pwm); dev(pwm)->SEQ[0].CNT = PWM_CHANNELS;
dev(pwm)->SEQ[0].REFRESH = 0; dev(pwm)->SEQ[0].REFRESH = 0;
dev(pwm)->SEQ[0].ENDDELAY = 0; dev(pwm)->SEQ[0].ENDDELAY = 0;

2
cpu/nrf5x_common/include/periph_cpu_common.h
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@ -55,6 +55,8 @@ extern "C" {
/** /**
* @brief Override GPIO_UNDEF value * @brief Override GPIO_UNDEF value
*/ */
/* The precise value matters where GPIO_UNDEF is set in registers like
* PWM.PSEL.OUT where it is used in sign-extended form to get a UINT32_MAX */
#define GPIO_UNDEF (UINT8_MAX) #define GPIO_UNDEF (UINT8_MAX)
/** /**