Merge pull request #15117 from chrysn-pull-requests/nrf52-pwm-fixes
cpu/nrf52: PWM fixes
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add0814cd0
@ -173,6 +173,10 @@ typedef enum {
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* @note define unused pins only from right to left, so the defined channels
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* always start with channel 0 to x and the undefined ones are from x+1
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* to PWM_CHANNELS.
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*
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* @warning All the channels not in active use must be set to GPIO_UNDEF; just
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* initializing fewer members of pin would insert a 0 value, which
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* would be interpreted as the P0.00 pin that's then driven.
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*/
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#if defined(PWM_PRESENT) || DOXYGEN
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typedef struct {
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@ -90,12 +90,12 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
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/* pin configuration */
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for (unsigned i = 0; i < PWM_CHANNELS; i++) {
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if (pwm_config[pwm].pin[i] != GPIO_UNDEF) {
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NRF_P0->PIN_CNF[pwm_config[pwm].pin[i]] = PIN_CNF_SET;
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}
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/* either left aligned pol or inverted duty cycle */
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pwm_seq[pwm][i] = (POL_MASK & mode) ? POL_MASK : res;
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dev(pwm)->PSEL.OUT[i] = pwm_config[pwm].pin[i];
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/* Sign-extend the undefined pin into a value that also sets the
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* 'Disconnected' field, and is also that register's reset state */
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uint32_t extended_pin = (int32_t)(int8_t)pwm_config[pwm].pin[i];
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dev(pwm)->PSEL.OUT[i] = extended_pin;
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DEBUG("set PIN[%i] to %i with 0x%x\n",
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(int)i, (int)pwm_config[pwm].pin[i], pwm_seq[pwm][i]);
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}
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@ -118,7 +118,7 @@ uint32_t pwm_init(pwm_t pwm, pwm_mode_t mode, uint32_t freq, uint16_t res)
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/* setup the sequence */
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dev(pwm)->SEQ[0].PTR = (uint32_t)pwm_seq[pwm];
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dev(pwm)->SEQ[0].CNT = pwm_channels(pwm);
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dev(pwm)->SEQ[0].CNT = PWM_CHANNELS;
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dev(pwm)->SEQ[0].REFRESH = 0;
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dev(pwm)->SEQ[0].ENDDELAY = 0;
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@ -55,6 +55,8 @@ extern "C" {
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/**
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* @brief Override GPIO_UNDEF value
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*/
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/* The precise value matters where GPIO_UNDEF is set in registers like
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* PWM.PSEL.OUT where it is used in sign-extended form to get a UINT32_MAX */
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#define GPIO_UNDEF (UINT8_MAX)
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/**
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