diff --git a/cpu/nrf52/include/cpu_conf.h b/cpu/nrf52/include/cpu_conf.h index 5b6b9a1697..06bce33457 100644 --- a/cpu/nrf52/include/cpu_conf.h +++ b/cpu/nrf52/include/cpu_conf.h @@ -66,14 +66,12 @@ extern "C" { * @brief Flash page configuration * @{ */ -#define FLASHPAGE_SIZE (4096U) - -#if defined(CPU_MODEL_NRF52811XXAA) -#define FLASHPAGE_NUMOF (48U) -#elif defined(CPU_MODEL_NRF52832XXAA) -#define FLASHPAGE_NUMOF (128U) +#ifdef BPROT_PRESENT +#define FLASHPAGE_SIZE BPROT_REGIONS_SIZE +#define FLASHPAGE_NUMOF BPROT_REGIONS_NUM #elif defined(CPU_MODEL_NRF52840XXAA) -#define FLASHPAGE_NUMOF (256U) +#define FLASHPAGE_SIZE (4096U) +#define FLASHPAGE_NUMOF (256U) #endif /* The minimum block size which can be written is 4B. However, the erase diff --git a/cpu/nrf52/include/vendor/nrf52.h b/cpu/nrf52/include/vendor/nrf52.h index c27077ff40..7147cfa1f3 100644 --- a/cpu/nrf52/include/vendor/nrf52.h +++ b/cpu/nrf52/include/vendor/nrf52.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +30,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 06. June 2018 - * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:38 + * @date 04. March 2020 + * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52 * from File 'nrf52.svd', - * last modified on Wednesday, 06.06.2018 13:21:34 + * last modified on Wednesday, 04.03.2020 13:56:43 */ @@ -128,10 +128,12 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -2415,7 +2417,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ -#elif (__ARMCC_VERSION >= 6010050) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ diff --git a/cpu/nrf52/include/vendor/nrf52811.h b/cpu/nrf52/include/vendor/nrf52811.h index 000099ceb9..0df982c006 100644 --- a/cpu/nrf52/include/vendor/nrf52811.h +++ b/cpu/nrf52/include/vendor/nrf52811.h @@ -129,7 +129,6 @@ typedef enum { /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ -#include "system_nrf52811.h" /*!< nrf52811 System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I diff --git a/cpu/nrf52/include/vendor/nrf52840.h b/cpu/nrf52/include/vendor/nrf52840.h index ba4c9b1117..49c7579e8f 100644 --- a/cpu/nrf52/include/vendor/nrf52840.h +++ b/cpu/nrf52/include/vendor/nrf52840.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +30,10 @@ * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 06. June 2018 - * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:39 + * @date 04. March 2020 + * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52 * from File 'nrf52840.svd', - * last modified on Wednesday, 06.06.2018 13:21:35 + * last modified on Wednesday, 04.03.2020 13:56:44 */ @@ -134,10 +134,12 @@ typedef enum { /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -199,8 +201,7 @@ typedef struct { __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ - __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ -} FICR_INFO_Type; /*!< Size = 32 (0x20) */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ /** @@ -233,16 +234,16 @@ typedef struct { typedef struct { __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ + NFCID1_2ND_LAST, and NFCID1_LAST. */ __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ + NFCID1_2ND_LAST, and NFCID1_LAST. */ __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ + NFCID1_2ND_LAST, and NFCID1_LAST. */ __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ + NFCID1_2ND_LAST, and NFCID1_LAST. */ } FICR_NFC_Type; /*!< Size = 16 (0x10) */ @@ -265,10 +266,9 @@ typedef struct { * @brief POWER_RAM [RAM] (Unspecified) */ typedef struct { - __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register */ - __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set - register */ - __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear register */ __IM uint32_t RESERVED; } POWER_RAM_Type; /*!< Size = 16 (0x10) */ @@ -388,7 +388,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ -} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ /** @@ -398,7 +399,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ -} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ /** @@ -457,7 +459,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ -} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ /** @@ -467,7 +470,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ -} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ /** @@ -497,13 +501,13 @@ typedef struct { /** - * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) */ typedef struct { - __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last result is equal - or above CH[n].LIMIT.HIGH */ - __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last result is equal - or below CH[n].LIMIT.LOW */ + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or + below CH[n].LIMIT.LOW */ } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ @@ -511,13 +515,13 @@ typedef struct { * @brief SAADC_CH [CH] (Unspecified) */ typedef struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection for CH[n] */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for CH[n] */ - __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event monitoring of a channel */ } SAADC_CH_Type; /*!< Size = 16 (0x10) */ @@ -548,15 +552,14 @@ typedef struct { * @brief PWM_SEQ [SEQ] (Unspecified) */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in - RAM of this sequence */ - __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty - cycles) in this sequence */ - __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional - PWM periods between samples loaded into - compare register */ - __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the - sequence */ + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ __IM uint32_t RESERVED[4]; } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ @@ -565,8 +568,8 @@ typedef struct { * @brief PWM_PSEL [PSEL] (Unspecified) */ typedef struct { - __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select - for PWM channel n */ + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ @@ -594,15 +597,15 @@ typedef struct { * @brief ACL_ACL [ACL] (Unspecified) */ typedef struct { - __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster[n]: Configure the word-aligned + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned start address of region n to protect */ - __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster[n]: Size of region to protect + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ - __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster[n]: Access permissions for - region n as defined by start address ACL[n].ADDR + __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region + n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ - __IOM uint32_t UNUSED0; /*!< (@ 0x0000000C) Unspecified */ + __IM uint32_t RESERVED; } ACL_ACL_Type; /*!< Size = 16 (0x10) */ @@ -610,10 +613,8 @@ typedef struct { * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) */ typedef struct { - __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group - n */ - __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group - n */ + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ @@ -621,8 +622,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -630,28 +631,28 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ /** - * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to region - n detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to region - n detected */ + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n + detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n + detected */ } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ /** - * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to peripheral + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral region n detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to peripheral + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral region n detected */ } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ @@ -660,11 +661,11 @@ typedef struct { * @brief MWU_PERREGION [PERREGION] (Unspecified) */ typedef struct { - __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[n]: Source of event/interrupt + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ - __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[n]: Source of event/interrupt + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ @@ -675,10 +676,9 @@ typedef struct { * @brief MWU_REGION [REGION] (Unspecified) */ typedef struct { - __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Start address for region - n */ - __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: End address of region + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region n */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ __IM uint32_t RESERVED[2]; } MWU_REGION_Type; /*!< Size = 16 (0x10) */ @@ -687,10 +687,9 @@ typedef struct { * @brief MWU_PREGION [PREGION] (Unspecified) */ typedef struct { - __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Reserved for future use */ - __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: Reserved for future use */ - __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[n]: Subregions of region - n */ + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ __IM uint32_t RESERVED; } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ @@ -752,13 +751,13 @@ typedef struct { * @brief USBD_HALTED [HALTED] (Unspecified) */ typedef struct { - __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection[n]: IN endpoint halted - status. Can be used as is as response to - a GetStatus() request to endpoint. */ + __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ __IM uint32_t RESERVED; - __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection[n]: OUT endpoint halted - status. Can be used as is as response to - a GetStatus() request to endpoint. */ + __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ @@ -766,7 +765,7 @@ typedef struct { * @brief USBD_SIZE [SIZE] (Unspecified) */ typedef struct { - __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection[n]: Number of bytes received + __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received last in the data stage of this OUT endpoint */ __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT data endpoint */ @@ -777,10 +776,10 @@ typedef struct { * @brief USBD_EPIN [EPIN] (Unspecified) */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred in the last transaction */ __IM uint32_t RESERVED[2]; } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ @@ -800,10 +799,10 @@ typedef struct { * @brief USBD_EPOUT [EPOUT] (Unspecified) */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred in the last transaction */ __IM uint32_t RESERVED[2]; } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ @@ -890,21 +889,20 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ __IM uint32_t RESERVED1[18]; - __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ __IM uint32_t RESERVED2[6]; - __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word - n */ - __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity Root, word + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ - __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ __IM uint32_t RESERVED3[21]; - __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ - __IM uint32_t RESERVED4[140]; - __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection[n]: Production test signature + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[143]; + __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature n */ __IM uint32_t RESERVED5[42]; - __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization coefficients */ __IM uint32_t RESERVED6[2]; __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ @@ -924,26 +922,24 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu */ typedef struct { /*!< (@ 0x10001000) UICR Structure */ - __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ - __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ - __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ - __IM uint32_t RESERVED; - __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ - __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic - firmware design */ - __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic - hardware design */ - __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ - __IM uint32_t RESERVED1[64]; - __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET - function */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET + function (see POWER chapter for details) */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ - __IM uint32_t RESERVED2[60]; - __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply - voltage in high voltage mode */ + __IM uint32_t RESERVED3[60]; + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The + maximum output voltage from this stage is + given as VDDH - VREG0DROP. */ } NRF_UICR_Type; /*!< Size = 776 (0x308) */ @@ -1015,8 +1011,8 @@ typedef struct { /*!< (@ 0x40000000) CLOCK Struct typedef struct { /*!< (@ 0x40000000) POWER Structure */ __IM uint32_t RESERVED[30]; - __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ - __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ __IM uint32_t RESERVED1[34]; __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ __IM uint32_t RESERVED2[2]; @@ -1042,9 +1038,9 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ __IM uint32_t RESERVED10[21]; - __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */ + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ __IM uint32_t RESERVED11; - __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */ + __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */ __IM uint32_t RESERVED12[47]; __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ __IM uint32_t RESERVED13[175]; @@ -1053,6 +1049,36 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + /* =========================================================================================================================== */ /* ================ RADIO ================ */ /* =========================================================================================================================== */ @@ -1112,10 +1138,10 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ __IM uint32_t RESERVED3[3]; __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and - BleIeee802154_250Kbit modes when last bit - is sent on air. */ + Ieee802154_250Kbit modes when last bit is + sent on air. */ __IM uint32_t RESERVED4[36]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED5[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1151,9 +1177,9 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IM uint32_t RESERVED11[2]; __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ __IM uint32_t RESERVED12[39]; - __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base - segment n */ - __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ @@ -1198,7 +1224,7 @@ typedef struct { /*!< (@ 0x40002000) UART0 Struct __IM uint32_t RESERVED4[7]; __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ __IM uint32_t RESERVED5[46]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED6[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1254,7 +1280,7 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IM uint32_t RESERVED6; __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ __IM uint32_t RESERVED7[41]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1337,7 +1363,7 @@ typedef struct { /*!< (@ 0x40003000) SPIM0 Struct __IM uint32_t RESERVED6[10]; __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ __IM uint32_t RESERVED7[44]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1391,7 +1417,7 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct __IM uint32_t RESERVED3[5]; __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ __IM uint32_t RESERVED4[53]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED5[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1405,14 +1431,12 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IM uint32_t RESERVED10[7]; __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ - __IM uint32_t RESERVED11; __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ - __IM uint32_t RESERVED12; __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED11; __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case of an ignored transaction. */ - __IM uint32_t RESERVED14[24]; + __IM uint32_t RESERVED12[24]; __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ @@ -1449,7 +1473,7 @@ typedef struct { /*!< (@ 0x40003000) TWI0 Structu __IM uint32_t RESERVED7[3]; __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ __IM uint32_t RESERVED8[45]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED9[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1505,7 +1529,7 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last byte */ __IM uint32_t RESERVED7[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1557,7 +1581,7 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ __IM uint32_t RESERVED7[37]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1572,15 +1596,13 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IM uint32_t RESERVED12[9]; __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IM uint32_t RESERVED13; __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED14[14]; - __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address - n */ - __IM uint32_t RESERVED15; + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match mechanism */ - __IM uint32_t RESERVED16[10]; + __IM uint32_t RESERVED15[10]; __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case of an over-read of the transmit buffer. */ } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ @@ -1640,7 +1662,7 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ __IM uint32_t RESERVED6[43]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED7[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1687,19 +1709,19 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu */ typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ - __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is configured in CONFIG[n].POLARITY. */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ __IM uint32_t RESERVED[4]; - __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is to set it high. */ + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ __IM uint32_t RESERVED1[4]; - __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is to set it low. */ + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ __IM uint32_t RESERVED2[32]; - __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from pin specified in CONFIG[n].PSEL */ __IM uint32_t RESERVED3[23]; __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins @@ -1708,9 +1730,8 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED5[129]; - __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for - OUT[n], SET[n] and CLR[n] tasks and IN[n] - event */ + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n] and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -1740,7 +1761,7 @@ typedef struct { /*!< (@ 0x40007000) SAADC Struct __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ - __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ __IM uint32_t RESERVED1[106]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1780,13 +1801,13 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ __IM uint32_t RESERVED[11]; - __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value - to CC[n] register */ + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ __IM uint32_t RESERVED1[58]; - __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] match */ __IM uint32_t RESERVED2[42]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1796,7 +1817,7 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc __IM uint32_t RESERVED5; __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ __IM uint32_t RESERVED6[11]; - __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register n */ } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ @@ -1820,7 +1841,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ __IM uint32_t RESERVED1[14]; - __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] match */ __IM uint32_t RESERVED2[109]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1834,7 +1855,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu t be written when RTC is stopped */ __IM uint32_t RESERVED5[13]; - __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1898,7 +1919,7 @@ typedef struct { /*!< (@ 0x4000D000) RNG Structur __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number written to the VALUE register */ __IM uint32_t RESERVED1[63]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1991,7 +2012,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -2036,7 +2057,7 @@ typedef struct { /*!< (@ 0x40010000) WDT Structur __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ __IM uint32_t RESERVED4[60]; - __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ @@ -2064,7 +2085,7 @@ typedef struct { /*!< (@ 0x40012000) QDEC Structu __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ __IM uint32_t RESERVED1[59]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -2109,7 +2130,7 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -2148,7 +2169,7 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -2177,10 +2198,10 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc */ typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ - __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ __IM uint32_t RESERVED[48]; - __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ __IM uint32_t RESERVED1[112]; @@ -2220,9 +2241,9 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ - __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM - value on all enabled channels from sequence - n, and starts playing that sequence at the + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on @@ -2232,16 +2253,16 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu __IM uint32_t RESERVED1[60]; __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no longer generated */ - __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started on sequence n */ - __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of - every sequence n, when last value from RAM - has been applied to wave counter */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount of times defined in LOOP.CNT */ __IM uint32_t RESERVED2[56]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -2366,7 +2387,7 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu */ typedef struct { /*!< (@ 0x4001F000) PPI Structure */ - __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ __IM uint32_t RESERVED[308]; __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ @@ -2374,7 +2395,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur __IM uint32_t RESERVED1; __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ __IM uint32_t RESERVED2[148]; - __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ __IM uint32_t RESERVED3[62]; __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ @@ -2392,17 +2413,17 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur typedef struct { /*!< (@ 0x40020000) MWU Structure */ __IM uint32_t RESERVED[64]; - __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ __IM uint32_t RESERVED1[16]; - __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ __IM uint32_t RESERVED2[100]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED3[5]; - __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ - __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ - __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ __IM uint32_t RESERVED4[53]; __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ __IM uint32_t RESERVED5[64]; @@ -2430,7 +2451,7 @@ typedef struct { /*!< (@ 0x40025000) I2S Structur __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. - Triggering this task will cause the {event:STOPPED} + Triggering this task will cause the STOPPED event to be generated. */ __IM uint32_t RESERVED[63]; __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal @@ -2490,14 +2511,14 @@ typedef struct { /*!< (@ 0x40026000) FPU Structur typedef struct { /*!< (@ 0x40027000) USBD Structure */ __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection[n]: Captures the EPIN[n].PTR + __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ - __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection[n]: Captures the EPOUT[n].PTR + __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ @@ -2519,18 +2540,18 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ - __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection[n]: The whole EPIN[n] - buffer has been consumed. The RAM buffer - can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place on the control endpoint */ __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The - RAM buffer can be accessed safely by software. */ - __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection[n]: The whole EPOUT[n] - buffer has been consumed. The RAM buffer - can be accessed safely by software. */ + buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The - RAM buffer can be accessed safely by software. */ + buffer can be accessed safely by software. */ __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition has been detected on USB lines */ __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific @@ -2541,7 +2562,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ __IM uint32_t RESERVED2[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -2648,36 +2669,6 @@ typedef struct { /*!< (@ 0x40029000) QSPI Structu -/* =========================================================================================================================== */ -/* ================ P0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief GPIO Port 1 (P0) - */ - -typedef struct { /*!< (@ 0x50000000) P0 Structure */ - __IM uint32_t RESERVED[321]; - __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ - __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ - __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ - __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ - __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ - __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ - __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ - __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that - have met the criteria set in the PIN_CNF[n].SENSE - registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour - and LDETECT mode */ - __IM uint32_t RESERVED1[118]; - __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO - pins */ -} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ - - - /* =========================================================================================================================== */ /* ================ CC_HOST_RGF ================ */ /* =========================================================================================================================== */ @@ -2747,6 +2738,8 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_UICR_BASE 0x10001000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL #define NRF_RADIO_BASE 0x40001000UL #define NRF_UART0_BASE 0x40002000UL #define NRF_UARTE0_BASE 0x40002000UL @@ -2810,12 +2803,10 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_USBD_BASE 0x40027000UL #define NRF_UARTE1_BASE 0x40028000UL #define NRF_QSPI_BASE 0x40029000UL -#define NRF_PWM3_BASE 0x4002D000UL -#define NRF_SPIM3_BASE 0x4002F000UL -#define NRF_P0_BASE 0x50000000UL -#define NRF_P1_BASE 0x50000300UL #define NRF_CC_HOST_RGF_BASE 0x5002A000UL #define NRF_CRYPTOCELL_BASE 0x5002A000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_SPIM3_BASE 0x4002F000UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -2833,6 +2824,8 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) @@ -2896,12 +2889,10 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) -#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) -#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) -#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) -#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) +#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ @@ -2911,7 +2902,7 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ -#elif (__ARMCC_VERSION >= 6010050) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ diff --git a/cpu/nrf52/include/vendor/nrf52840_bitfields.h b/cpu/nrf52/include/vendor/nrf52840_bitfields.h index 6d1990bb1e..b4302ffd09 100644 --- a/cpu/nrf52/include/vendor/nrf52840_bitfields.h +++ b/cpu/nrf52/include/vendor/nrf52840_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -41,56 +41,64 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_TASKS_START */ /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ -/* Bit 0 : */ +/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_TASKS_STOP */ /* Description: Stop resolving addresses */ -/* Bit 0 : */ +/* Bit 0 : Stop resolving addresses */ #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_EVENTS_END */ /* Description: Address resolution procedure complete */ -/* Bit 0 : */ +/* Bit 0 : Address resolution procedure complete */ #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_RESOLVED */ /* Description: Address resolved */ -/* Bit 0 : */ +/* Bit 0 : Address resolved */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_NOTRESOLVED */ /* Description: Address not resolved */ -/* Bit 0 : */ +/* Bit 0 : Address not resolved */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for END event */ +/* Bit 0 : Write '1' to enable interrupt for event END */ #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -100,21 +108,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for END event */ +/* Bit 0 : Write '1' to disable interrupt for event END */ #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -170,21 +178,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access control lists */ /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster[n]: Configure the word-aligned start address of region n to protect */ +/* Description: Description cluster: Configure the word-aligned start address of region n to protect */ /* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ /* Register: ACL_ACL_PERM */ -/* Description: Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ +/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ /* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ @@ -205,56 +213,66 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_TASKS_KSGEN */ /* Description: Start generation of key-stream. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_CRYPT */ /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_STOP */ /* Description: Stop encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Stop encryption/decryption */ #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_RATEOVERRIDE */ /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ /* Description: Key-stream generation complete */ -/* Bit 0 : */ +/* Bit 0 : Key-stream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ENDCRYPT */ /* Description: Encrypt/decrypt complete */ -/* Bit 0 : */ +/* Bit 0 : Encrypt/decrypt complete */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ERROR */ /* Description: Deprecated register - CCM error event */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - CCM error event */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: CCM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ @@ -263,21 +281,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for ERROR event */ +/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -287,21 +305,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for ERROR event */ +/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -469,133 +487,152 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_TASKS_HFCLKSTART */ /* Description: Start HFXO crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Start HFXO crystal oscillator */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_HFCLKSTOP */ /* Description: Stop HFXO crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Stop HFXO crystal oscillator */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTART */ /* Description: Start LFCLK */ -/* Bit 0 : */ +/* Bit 0 : Start LFCLK */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTOP */ /* Description: Stop LFCLK */ -/* Bit 0 : */ +/* Bit 0 : Stop LFCLK */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CAL */ /* Description: Start calibration of LFRC */ -/* Bit 0 : */ +/* Bit 0 : Start calibration of LFRC */ #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTART */ /* Description: Start calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Start calibration timer */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTOP */ /* Description: Stop calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Stop calibration timer */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_EVENTS_HFCLKSTARTED */ /* Description: HFXO crystal oscillator started */ -/* Bit 0 : */ +/* Bit 0 : HFXO crystal oscillator started */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_LFCLKSTARTED */ /* Description: LFCLK started */ -/* Bit 0 : */ +/* Bit 0 : LFCLK started */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_DONE */ /* Description: Calibration of LFRC completed */ -/* Bit 0 : */ +/* Bit 0 : Calibration of LFRC completed */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTTO */ /* Description: Calibration timer timeout */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer timeout */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTSTARTED */ /* Description: Calibration timer has been started and is ready to process new tasks */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer has been started and is ready to process new tasks */ #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */ #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTSTOPPED */ /* Description: Calibration timer has been stopped and is ready to process new tasks */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */ #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */ #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ -/* Bit 11 : Write '1' to enable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */ #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */ #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for CTTO event */ +/* Bit 4 : Write '1' to enable interrupt for event CTTO */ #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DONE event */ +/* Bit 3 : Write '1' to enable interrupt for event DONE */ #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -605,42 +642,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 11 : Write '1' to disable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */ #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */ #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for CTTO event */ +/* Bit 4 : Write '1' to disable interrupt for event CTTO */ #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DONE event */ +/* Bit 3 : Write '1' to disable interrupt for event DONE */ #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -784,80 +821,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_TASKS_START */ /* Description: Start comparator */ -/* Bit 0 : */ +/* Bit 0 : Start comparator */ #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_STOP */ /* Description: Stop comparator */ -/* Bit 0 : */ +/* Bit 0 : Stop comparator */ #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_SAMPLE */ /* Description: Sample comparator value */ -/* Bit 0 : */ +/* Bit 0 : Sample comparator value */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_EVENTS_READY */ /* Description: COMP is ready and output is valid */ -/* Bit 0 : */ +/* Bit 0 : COMP is ready and output is valid */ #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_DOWN */ /* Description: Downward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward crossing */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_UP */ /* Description: Upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Upward crossing */ #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_CROSS */ /* Description: Downward or upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward or upward crossing */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ /* Register: COMP_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between CROSS event and STOP task */ +/* Bit 4 : Shortcut between event CROSS and task STOP */ #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between UP event and STOP task */ +/* Bit 3 : Shortcut between event UP and task STOP */ #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DOWN event and STOP task */ +/* Bit 2 : Shortcut between event DOWN and task STOP */ #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between READY event and STOP task */ +/* Bit 1 : Shortcut between event READY and task STOP */ #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and SAMPLE task */ +/* Bit 0 : Shortcut between event READY and task SAMPLE */ #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -866,25 +914,25 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 3 : Enable or disable interrupt for CROSS event */ +/* Bit 3 : Enable or disable interrupt for event CROSS */ #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for UP event */ +/* Bit 2 : Enable or disable interrupt for event UP */ #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for DOWN event */ +/* Bit 1 : Enable or disable interrupt for event DOWN */ #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -893,28 +941,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for event UP */ #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -924,28 +972,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for event UP */ #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -1068,42 +1116,48 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_TASKS_STARTECB */ /* Description: Start ECB block encrypt */ -/* Bit 0 : */ +/* Bit 0 : Start ECB block encrypt */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_TASKS_STOPECB */ /* Description: Abort a possible executing ECB operation */ -/* Bit 0 : */ +/* Bit 0 : Abort a possible executing ECB operation */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_EVENTS_ENDECB */ /* Description: ECB block encrypt complete */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt complete */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_EVENTS_ERRORECB */ /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_INTENSET */ /* Description: Enable interrupt */ -/* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1113,14 +1167,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1139,113 +1193,116 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Event Generator Unit 0 */ /* Register: EGU_TASKS_TRIGGER */ -/* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ -/* Bit 0 : */ +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ /* Register: EGU_EVENTS_TRIGGERED */ -/* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ -/* Bit 0 : */ +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ /* Register: EGU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ @@ -1254,112 +1311,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1369,112 +1426,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1500,21 +1557,21 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ /* Register: FICR_DEVICEID */ -/* Description: Description collection[n]: Device identifier */ +/* Description: Description collection: Device identifier */ /* Bits 31..0 : 64 bit unique device identifier */ #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ /* Register: FICR_ER */ -/* Description: Description collection[n]: Encryption root, word n */ +/* Description: Description collection: Encryption root, word n */ /* Bits 31..0 : Encryption root, word n */ #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ /* Register: FICR_IR */ -/* Description: Description collection[n]: Identity Root, word n */ +/* Description: Description collection: Identity Root, word n */ /* Bits 31..0 : Identity Root, word n */ #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ @@ -1530,7 +1587,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ /* Register: FICR_DEVICEADDR */ -/* Description: Description collection[n]: Device address n */ +/* Description: Description collection: Device address n */ /* Bits 31..0 : 48 bit device address */ #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ @@ -1542,6 +1599,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part code */ #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */ #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1567,6 +1625,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -1596,7 +1655,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_PRODTEST */ -/* Description: Description collection[n]: Production test signature n */ +/* Description: Description collection: Production test signature n */ /* Bits 31..0 : Production test signature n */ #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ @@ -1724,7 +1783,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ /* Register: FICR_NFC_TAGHEADER0 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 3 */ #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ @@ -1743,7 +1802,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ /* Register: FICR_NFC_TAGHEADER1 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 7 */ #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ @@ -1762,7 +1821,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ /* Register: FICR_NFC_TAGHEADER2 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 11 */ #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ @@ -1781,7 +1840,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ /* Register: FICR_NFC_TAGHEADER3 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 15 */ #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ @@ -1860,100 +1919,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: GPIO Tasks and Events */ /* Register: GPIOTE_TASKS_OUT */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_SET */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_CLR */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_EVENTS_IN */ -/* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ -/* Bit 0 : */ +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_EVENTS_PORT */ /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ -/* Bit 0 : */ +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 31 : Write '1' to enable interrupt for PORT event */ +/* Bit 31 : Write '1' to enable interrupt for event PORT */ #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -1963,63 +2029,63 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIOTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 31 : Write '1' to disable interrupt for PORT event */ +/* Bit 31 : Write '1' to disable interrupt for event PORT */ #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -2027,7 +2093,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -2065,56 +2131,66 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_TASKS_START */ /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ -/* Bit 0 : */ +/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: I2S_TASKS_STOP */ -/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */ +/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ -/* Bit 0 : */ +/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: I2S_EVENTS_RXPTRUPD */ /* Description: The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ -/* Bit 0 : */ +/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ /* Register: I2S_EVENTS_STOPPED */ /* Description: I2S transfer stopped. */ -/* Bit 0 : */ +/* Bit 0 : I2S transfer stopped. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: I2S_EVENTS_TXPTRUPD */ /* Description: The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ -/* Bit 0 : */ +/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ /* Register: I2S_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for STOPPED event */ +/* Bit 2 : Enable or disable interrupt for event STOPPED */ #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ @@ -2123,21 +2199,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENSET */ /* Description: Enable interrupt */ -/* Bit 5 : Write '1' to enable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to enable interrupt for event STOPPED */ #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2147,21 +2223,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 5 : Write '1' to disable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to disable interrupt for event STOPPED */ #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2232,11 +2308,6 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ /* Register: I2S_CONFIG_RATIO */ /* Description: MCK / LRCK ratio. */ @@ -2405,80 +2476,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_TASKS_START */ /* Description: Start comparator */ -/* Bit 0 : */ +/* Bit 0 : Start comparator */ #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_TASKS_STOP */ /* Description: Stop comparator */ -/* Bit 0 : */ +/* Bit 0 : Stop comparator */ #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_TASKS_SAMPLE */ /* Description: Sample comparator value */ -/* Bit 0 : */ +/* Bit 0 : Sample comparator value */ #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_EVENTS_READY */ /* Description: LPCOMP is ready and output is valid */ -/* Bit 0 : */ +/* Bit 0 : LPCOMP is ready and output is valid */ #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_DOWN */ /* Description: Downward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward crossing */ #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_UP */ /* Description: Upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Upward crossing */ #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_CROSS */ /* Description: Downward or upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward or upward crossing */ #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between CROSS event and STOP task */ +/* Bit 4 : Shortcut between event CROSS and task STOP */ #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between UP event and STOP task */ +/* Bit 3 : Shortcut between event UP and task STOP */ #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DOWN event and STOP task */ +/* Bit 2 : Shortcut between event DOWN and task STOP */ #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between READY event and STOP task */ +/* Bit 1 : Shortcut between event READY and task STOP */ #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and SAMPLE task */ +/* Bit 0 : Shortcut between event READY and task SAMPLE */ #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -2487,28 +2569,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for event UP */ #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2518,28 +2600,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for event UP */ #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2635,103 +2717,111 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Memory Watch Unit */ /* Register: MWU_EVENTS_REGION_WA */ -/* Description: Description cluster[n]: Write access to region n detected */ +/* Description: Description cluster: Write access to region n detected */ -/* Bit 0 : */ +/* Bit 0 : Write access to region n detected */ #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_REGION_RA */ -/* Description: Description cluster[n]: Read access to region n detected */ +/* Description: Description cluster: Read access to region n detected */ -/* Bit 0 : */ +/* Bit 0 : Read access to region n detected */ #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_PREGION_WA */ -/* Description: Description cluster[n]: Write access to peripheral region n detected */ +/* Description: Description cluster: Write access to peripheral region n detected */ -/* Bit 0 : */ +/* Bit 0 : Write access to peripheral region n detected */ #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_PREGION_RA */ -/* Description: Description cluster[n]: Read access to peripheral region n detected */ +/* Description: Description cluster: Read access to peripheral region n detected */ -/* Bit 0 : */ +/* Bit 0 : Read access to peripheral region n detected */ #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ #define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */ /* Register: MWU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ @@ -2740,84 +2830,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2827,84 +2917,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2912,161 +3002,161 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_NMIEN */ -/* Description: Enable or disable non-maskable interrupt */ +/* Description: Enable or disable interrupt */ -/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ /* Register: MWU_NMIENSET */ -/* Description: Enable non-maskable interrupt */ +/* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3074,86 +3164,86 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ /* Register: MWU_NMIENCLR */ -/* Description: Disable non-maskable interrupt */ +/* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3161,7 +3251,7 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_PERREGION_SUBSTATWA */ -/* Description: Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ /* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -3356,7 +3446,7 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ /* Register: MWU_PERREGION_SUBSTATRA */ -/* Description: Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ /* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -3800,35 +3890,35 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ /* Register: MWU_REGION_START */ -/* Description: Description cluster[n]: Start address for region n */ +/* Description: Description cluster: Start address for region n */ /* Bits 31..0 : Start address for region */ #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_REGION_END */ -/* Description: Description cluster[n]: End address of region n */ +/* Description: Description cluster: End address of region n */ /* Bits 31..0 : End address of region. */ #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_START */ -/* Description: Description cluster[n]: Reserved for future use */ +/* Description: Description cluster: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_PREGION_END */ -/* Description: Description cluster[n]: Reserved for future use */ +/* Description: Description cluster: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_SUBS */ -/* Description: Description cluster[n]: Subregions of region n */ +/* Description: Description cluster: Subregions of region n */ /* Bit 31 : Include or exclude subregion 31 in region */ #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -4029,173 +4119,210 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_TASKS_ACTIVATE */ /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ -/* Bit 0 : */ +/* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_DISABLE */ /* Description: Disable NFCT peripheral */ -/* Bit 0 : */ +/* Bit 0 : Disable NFCT peripheral */ #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_SENSE */ /* Description: Enable NFC sense field mode, change state to sense mode */ -/* Bit 0 : */ +/* Bit 0 : Enable NFC sense field mode, change state to sense mode */ #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */ #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_STARTTX */ /* Description: Start transmission of an outgoing frame, change state to transmit */ -/* Bit 0 : */ +/* Bit 0 : Start transmission of an outgoing frame, change state to transmit */ #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_ENABLERXDATA */ /* Description: Initializes the EasyDMA for receive. */ -/* Bit 0 : */ +/* Bit 0 : Initializes the EasyDMA for receive. */ #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */ #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_GOIDLE */ /* Description: Force state machine to IDLE state */ -/* Bit 0 : */ +/* Bit 0 : Force state machine to IDLE state */ #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */ #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_GOSLEEP */ /* Description: Force state machine to SLEEP_A state */ -/* Bit 0 : */ +/* Bit 0 : Force state machine to SLEEP_A state */ #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */ #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_EVENTS_READY */ /* Description: The NFCT peripheral is ready to receive and send frames */ -/* Bit 0 : */ +/* Bit 0 : The NFCT peripheral is ready to receive and send frames */ #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_FIELDDETECTED */ /* Description: Remote NFC field detected */ -/* Bit 0 : */ +/* Bit 0 : Remote NFC field detected */ #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */ #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_FIELDLOST */ /* Description: Remote NFC field lost */ -/* Bit 0 : */ +/* Bit 0 : Remote NFC field lost */ #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */ #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_TXFRAMESTART */ /* Description: Marks the start of the first symbol of a transmitted frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the start of the first symbol of a transmitted frame */ #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */ #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_TXFRAMEEND */ /* Description: Marks the end of the last transmitted on-air symbol of a frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */ #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */ #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXFRAMESTART */ /* Description: Marks the end of the first symbol of a received frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the end of the first symbol of a received frame */ #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */ #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXFRAMEEND */ /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ -/* Bit 0 : */ +/* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */ #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ERROR */ /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ -/* Bit 0 : */ +/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXERROR */ /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ -/* Bit 0 : */ +/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */ #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ENDRX */ /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ -/* Bit 0 : */ +/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ENDTX */ /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ -/* Bit 0 : */ +/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */ /* Description: Auto collision resolution process has started */ -/* Bit 0 : */ +/* Bit 0 : Auto collision resolution process has started */ #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */ #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_COLLISION */ /* Description: NFC auto collision resolution error reported. */ -/* Bit 0 : */ +/* Bit 0 : NFC auto collision resolution error reported. */ #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */ #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_SELECTED */ /* Description: NFC auto collision resolution successfully completed */ -/* Bit 0 : */ +/* Bit 0 : NFC auto collision resolution successfully completed */ #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */ #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_STARTED */ /* Description: EasyDMA is ready to receive or send frames. */ -/* Bit 0 : */ +/* Bit 0 : EasyDMA is ready to receive or send frames. */ #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */ +/* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */ #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ @@ -4204,91 +4331,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 20 : Enable or disable interrupt for STARTED event */ +/* Bit 20 : Enable or disable interrupt for event STARTED */ #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for SELECTED event */ +/* Bit 19 : Enable or disable interrupt for event SELECTED */ #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for COLLISION event */ +/* Bit 18 : Enable or disable interrupt for event COLLISION */ #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for ENDTX event */ +/* Bit 12 : Enable or disable interrupt for event ENDTX */ #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for ENDRX event */ +/* Bit 11 : Enable or disable interrupt for event ENDRX */ #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for RXERROR event */ +/* Bit 10 : Enable or disable interrupt for event RXERROR */ #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for ERROR event */ +/* Bit 7 : Enable or disable interrupt for event ERROR */ #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */ #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */ #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */ #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */ #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +/* Bit 2 : Enable or disable interrupt for event FIELDLOST */ #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */ #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -4297,105 +4424,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 20 : Write '1' to enable interrupt for STARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event STARTED */ #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to enable interrupt for event SELECTED */ #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to enable interrupt for event COLLISION */ #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to enable interrupt for event ENDTX */ #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to enable interrupt for event ENDRX */ #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to enable interrupt for event RXERROR */ #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for ERROR event */ +/* Bit 7 : Write '1' to enable interrupt for event ERROR */ #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */ #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */ #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */ #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */ #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */ #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */ #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4405,105 +4532,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 20 : Write '1' to disable interrupt for STARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event STARTED */ #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to disable interrupt for event SELECTED */ #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to disable interrupt for event COLLISION */ #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to disable interrupt for event ENDTX */ #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to disable interrupt for event ENDRX */ #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to disable interrupt for event RXERROR */ #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for ERROR event */ +/* Bit 7 : Write '1' to disable interrupt for event ERROR */ #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */ #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */ #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */ #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */ #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */ #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */ #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -6615,7 +6742,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ /* Register: GPIO_PIN_CNF */ -/* Description: Description collection[n]: Configuration of GPIO pins */ +/* Description: Description collection: Configuration of GPIO pins */ /* Bits 17..16 : Pin sensing mechanism */ #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ @@ -6662,54 +6789,62 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_TASKS_START */ /* Description: Starts continuous PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Starts continuous PDM transfer */ #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_TASKS_STOP */ /* Description: Stops PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Stops PDM transfer */ #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_EVENTS_STARTED */ /* Description: PDM transfer has started */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has started */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_STOPPED */ /* Description: PDM transfer has finished */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has finished */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_END */ /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ -/* Bit 0 : */ +/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: PDM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 2 : Enable or disable interrupt for END event */ +/* Bit 2 : Enable or disable interrupt for event END */ #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -6718,21 +6853,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for END event */ +/* Bit 2 : Write '1' to enable interrupt for event END */ #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6742,21 +6877,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for END event */ +/* Bit 2 : Write '1' to disable interrupt for event END */ #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6882,100 +7017,114 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Power control */ /* Register: POWER_TASKS_CONSTLAT */ -/* Description: Enable constant latency mode */ +/* Description: Enable Constant Latency mode */ -/* Bit 0 : */ +/* Bit 0 : Enable Constant Latency mode */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ -/* Description: Enable low power mode (variable latency) */ +/* Description: Enable Low-power mode (variable latency) */ -/* Bit 0 : */ +/* Bit 0 : Enable Low-power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_EVENTS_POFWARN */ /* Description: Power failure warning */ -/* Bit 0 : */ +/* Bit 0 : Power failure warning */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPENTER */ /* Description: CPU entered WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU entered WFI/WFE sleep */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPEXIT */ /* Description: CPU exited WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU exited WFI/WFE sleep */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBDETECTED */ /* Description: Voltage supply detected on VBUS */ -/* Bit 0 : */ +/* Bit 0 : Voltage supply detected on VBUS */ #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */ #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBREMOVED */ /* Description: Voltage supply removed from VBUS */ -/* Bit 0 : */ +/* Bit 0 : Voltage supply removed from VBUS */ #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */ #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBPWRRDY */ /* Description: USB 3.3 V supply ready */ -/* Bit 0 : */ +/* Bit 0 : USB 3.3 V supply ready */ #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */ #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */ /* Register: POWER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 9 : Write '1' to enable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */ #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */ #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */ #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -6985,42 +7134,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 9 : Write '1' to disable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */ #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */ #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */ #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -7194,7 +7343,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ /* Register: POWER_DCDCEN */ -/* Description: Enable DC/DC converter for REG1 stage. */ +/* Description: Enable DC/DC converter for REG1 stage */ /* Bit 0 : Enable DC/DC converter for REG1 stage. */ #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ @@ -7203,7 +7352,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ /* Register: POWER_DCDCEN0 */ -/* Description: Enable DC/DC converter for REG0 stage. */ +/* Description: Enable DC/DC converter for REG0 stage */ /* Bit 0 : Enable DC/DC converter for REG0 stage. */ #define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ @@ -7221,7 +7370,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ /* Register: POWER_RAM_POWER */ -/* Description: Description cluster[n]: RAMn power control register */ +/* Description: Description cluster: RAMn power control register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is off */ #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7416,7 +7565,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERSET */ -/* Description: Description cluster[n]: RAMn power control set register */ +/* Description: Description cluster: RAMn power control set register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7579,7 +7728,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERCLR */ -/* Description: Description cluster[n]: RAMn power control clear register */ +/* Description: Description cluster: RAMn power control clear register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7746,18 +7895,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Programmable Peripheral Interconnect */ /* Register: PPI_TASKS_CHG_EN */ -/* Description: Description cluster[n]: Enable channel group n */ +/* Description: Description cluster: Enable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Enable channel group n */ #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_TASKS_CHG_DIS */ -/* Description: Description cluster[n]: Disable channel group n */ +/* Description: Description cluster: Disable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Disable channel group n */ #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_CHEN */ /* Description: Channel enable register */ @@ -8409,21 +8560,21 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster[n]: Channel n event end-point */ +/* Description: Description cluster: Channel n event end-point */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task end-point */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ /* Register: PPI_CHG */ -/* Description: Description collection[n]: Channel group n */ +/* Description: Description collection: Channel group n */ /* Bit 31 : Include or exclude channel 31 */ #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ @@ -8618,7 +8769,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task end-point */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -8631,87 +8782,100 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_TASKS_STOP */ /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ -/* Bit 0 : */ +/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_SEQSTART */ -/* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_NEXTSTEP */ /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_EVENTS_STOPPED */ /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ -/* Bit 0 : */ +/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQSTARTED */ -/* Description: Description collection[n]: First PWM period started on sequence n */ +/* Description: Description collection: First PWM period started on sequence n */ -/* Bit 0 : */ +/* Bit 0 : First PWM period started on sequence n */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQEND */ -/* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ +/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ -/* Bit 0 : */ +/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_PWMPERIODEND */ /* Description: Emitted at the end of each PWM period */ -/* Bit 0 : */ +/* Bit 0 : Emitted at the end of each PWM period */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_LOOPSDONE */ /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ -/* Bit 0 : */ +/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ /* Register: PWM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -8720,43 +8884,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -8765,49 +8929,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8817,49 +8981,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8932,14 +9096,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[n]: Beginning address in RAM of this sequence */ +/* Description: Description cluster: Beginning address in RAM of this sequence */ /* Bits 31..0 : Beginning address in RAM of this sequence */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ +/* Description: Description cluster: Number of values (duty cycles) in this sequence */ /* Bits 14..0 : Number of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8947,7 +9111,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ +/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8955,14 +9119,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ /* Register: PWM_SEQ_ENDDELAY */ -/* Description: Description cluster[n]: Time added after the sequence */ +/* Description: Description cluster: Time added after the sequence */ /* Bits 23..0 : Time added after the sequence in PWM periods */ #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: PWM_PSEL_OUT */ -/* Description: Description collection[n]: Output pin select for PWM channel n */ +/* Description: Description collection: Output pin select for PWM channel n */ /* Bit 31 : Connection */ #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8985,113 +9149,128 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_TASKS_START */ /* Description: Task starting the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task starting the quadrature decoder */ #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_STOP */ /* Description: Task stopping the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the quadrature decoder */ #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_READCLRACC */ /* Description: Read and clear ACC and ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC and ACCDBL */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRACC */ /* Description: Read and clear ACC */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRDBL */ /* Description: Read and clear ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACCDBL */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_EVENTS_SAMPLERDY */ /* Description: Event being generated for every new sample value written to the SAMPLE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_REPORTRDY */ /* Description: Non-null report ready */ -/* Bit 0 : */ +/* Bit 0 : Non-null report ready */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_ACCOF */ /* Description: ACC or ACCDBL register overflow */ -/* Bit 0 : */ +/* Bit 0 : ACC or ACCDBL register overflow */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_DBLRDY */ /* Description: Double displacement(s) detected */ -/* Bit 0 : */ +/* Bit 0 : Double displacement(s) detected */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_STOPPED */ /* Description: QDEC has been stopped */ -/* Bit 0 : */ +/* Bit 0 : QDEC has been stopped */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: QDEC_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ @@ -9100,35 +9279,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 4 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9138,35 +9317,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 4 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9334,49 +9513,56 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_TASKS_ACTIVATE */ /* Description: Activate QSPI interface */ -/* Bit 0 : */ +/* Bit 0 : Activate QSPI interface */ #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_READSTART */ /* Description: Start transfer from external flash memory to internal RAM */ -/* Bit 0 : */ +/* Bit 0 : Start transfer from external flash memory to internal RAM */ #define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */ #define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_WRITESTART */ /* Description: Start transfer from internal RAM to external flash memory */ -/* Bit 0 : */ +/* Bit 0 : Start transfer from internal RAM to external flash memory */ #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */ #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_ERASESTART */ /* Description: Start external flash memory erase operation */ -/* Bit 0 : */ +/* Bit 0 : Start external flash memory erase operation */ #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */ #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_DEACTIVATE */ /* Description: Deactivate QSPI interface */ -/* Bit 0 : */ +/* Bit 0 : Deactivate QSPI interface */ #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */ #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_EVENTS_READY */ /* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ -/* Bit 0 : */ +/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: QSPI_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -9385,7 +9571,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9395,7 +9581,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9428,9 +9614,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_READ_CNT */ /* Description: Read transfer length */ -/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 17..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_READ_CNT_CNT_Msk (0x3FFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_WRITE_DST */ /* Description: Flash destination address */ @@ -9449,9 +9635,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_WRITE_CNT */ /* Description: Write transfer length */ -/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 17..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_WRITE_CNT_CNT_Msk (0x3FFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_ERASE_PTR */ /* Description: Start address of flash block to be erased */ @@ -9808,360 +9994,417 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TASKS_TXEN */ /* Description: Enable RADIO in TX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in TX mode */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RXEN */ /* Description: Enable RADIO in RX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in RX mode */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_START */ /* Description: Start RADIO */ -/* Bit 0 : */ +/* Bit 0 : Start RADIO */ #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_STOP */ /* Description: Stop RADIO */ -/* Bit 0 : */ +/* Bit 0 : Stop RADIO */ #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_DISABLE */ /* Description: Disable RADIO */ -/* Bit 0 : */ +/* Bit 0 : Disable RADIO */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTART */ /* Description: Start the RSSI and take one single sample of the receive signal strength */ -/* Bit 0 : */ +/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTOP */ /* Description: Stop the RSSI measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop the RSSI measurement */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTART */ /* Description: Start the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Start the bit counter */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTOP */ /* Description: Stop the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Stop the bit counter */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_EDSTART */ /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ -/* Bit 0 : */ +/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_EDSTOP */ /* Description: Stop the energy detect measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop the energy detect measurement */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_CCASTART */ /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ -/* Bit 0 : */ +/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_CCASTOP */ /* Description: Stop the clear channel assessment */ -/* Bit 0 : */ +/* Bit 0 : Stop the clear channel assessment */ #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_EVENTS_READY */ /* Description: RADIO has ramped up and is ready to be started */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started */ #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_ADDRESS */ /* Description: Address sent or received */ -/* Bit 0 : */ +/* Bit 0 : Address sent or received */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_PAYLOAD */ /* Description: Packet payload sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet payload sent or received */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_END */ /* Description: Packet sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet sent or received */ #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DISABLED */ /* Description: RADIO has been disabled */ -/* Bit 0 : */ +/* Bit 0 : RADIO has been disabled */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMATCH */ /* Description: A device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : A device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMISS */ /* Description: No device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : No device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RSSIEND */ /* Description: Sampling of receive signal strength complete */ -/* Bit 0 : */ +/* Bit 0 : Sampling of receive signal strength complete */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_BCMATCH */ /* Description: Bit counter reached bit count value */ -/* Bit 0 : */ +/* Bit 0 : Bit counter reached bit count value */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCOK */ /* Description: Packet received with CRC ok */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC ok */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCERROR */ /* Description: Packet received with CRC error */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC error */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_FRAMESTART */ /* Description: IEEE 802.15.4 length field received */ -/* Bit 0 : */ +/* Bit 0 : IEEE 802.15.4 length field received */ #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDSTOPPED */ /* Description: The sampling of energy detection has stopped */ -/* Bit 0 : */ +/* Bit 0 : The sampling of energy detection has stopped */ #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCAIDLE */ /* Description: Wireless medium in idle - clear to send */ -/* Bit 0 : */ +/* Bit 0 : Wireless medium in idle - clear to send */ #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCABUSY */ /* Description: Wireless medium busy - do not send */ -/* Bit 0 : */ +/* Bit 0 : Wireless medium busy - do not send */ #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCASTOPPED */ /* Description: The CCA has stopped */ -/* Bit 0 : */ +/* Bit 0 : The CCA has stopped */ #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RATEBOOST */ /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ -/* Bit 0 : */ +/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_TXREADY */ /* Description: RADIO has ramped up and is ready to be started TX path */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started TX path */ #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RXREADY */ /* Description: RADIO has ramped up and is ready to be started RX path */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started RX path */ #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_MHRMATCH */ /* Description: MAC header match found */ -/* Bit 0 : */ +/* Bit 0 : MAC header match found */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_PHYEND */ -/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. */ +/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ -/* Bit 0 : */ +/* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 21 : Shortcut between PHYEND event and START task */ +/* Bit 21 : Shortcut between event PHYEND and task START */ #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 20 : Shortcut between PHYEND event and DISABLE task */ +/* Bit 20 : Shortcut between event PHYEND and task DISABLE */ #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 19 : Shortcut between RXREADY event and START task */ +/* Bit 19 : Shortcut between event RXREADY and task START */ #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 18 : Shortcut between TXREADY event and START task */ +/* Bit 18 : Shortcut between event TXREADY and task START */ #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 17 : Shortcut between CCAIDLE event and STOP task */ +/* Bit 17 : Shortcut between event CCAIDLE and task STOP */ #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 16 : Shortcut between EDEND event and DISABLE task */ +/* Bit 16 : Shortcut between event EDEND and task DISABLE */ #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 15 : Shortcut between READY event and EDSTART task */ +/* Bit 15 : Shortcut between event READY and task EDSTART */ #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */ +/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */ +/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */ +/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between RXREADY event and CCASTART task */ +/* Bit 11 : Shortcut between event RXREADY and task CCASTART */ #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between END event and START task */ +/* Bit 5 : Shortcut between event END and task START */ #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +/* Bit 3 : Shortcut between event DISABLED and task RXEN */ #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +/* Bit 2 : Shortcut between event DISABLED and task TXEN */ #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between END event and DISABLE task */ +/* Bit 1 : Shortcut between event END and task DISABLE */ #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and START task */ +/* Bit 0 : Shortcut between event READY and task START */ #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ @@ -10170,154 +10413,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to enable interrupt for event PHYEND */ #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for MHRMATCH event */ +/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to enable interrupt for event RXREADY */ #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to enable interrupt for event TXREADY */ #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for EDEND event */ +/* Bit 15 : Write '1' to enable interrupt for event EDEND */ #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for END event */ +/* Bit 3 : Write '1' to enable interrupt for event END */ #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10327,154 +10570,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to disable interrupt for event PHYEND */ #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for MHRMATCH event */ +/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to disable interrupt for event RXREADY */ #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to disable interrupt for event TXREADY */ #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for EDEND event */ +/* Bit 15 : Write '1' to disable interrupt for event EDEND */ #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for END event */ +/* Bit 3 : Write '1' to disable interrupt for event END */ #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10561,12 +10804,12 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ @@ -10839,14 +11082,14 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ /* Register: RADIO_DAB */ -/* Description: Description collection[n]: Device address base segment n */ +/* Description: Description collection: Device address base segment n */ /* Bits 31..0 : Device address base segment n */ #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ /* Register: RADIO_DAP */ -/* Description: Description collection[n]: Device address prefix n */ +/* Description: Description collection: Device address prefix n */ /* Bits 15..0 : Device address prefix n */ #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ @@ -10935,6 +11178,20 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ +/* Register: RADIO_MHRMATCHCONF */ +/* Description: Search pattern configuration */ + +/* Bits 31..0 : Search pattern configuration */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ + +/* Register: RADIO_MHRMATCHMAS */ +/* Description: Pattern mask */ + +/* Bits 31..0 : Pattern mask */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ + /* Register: RADIO_MODECNF0 */ /* Description: Radio mode configuration register 0 */ @@ -10948,8 +11205,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Radio ramp-up time */ #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ -#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -11012,28 +11269,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_TASKS_START */ /* Description: Task starting the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task starting the random number generator */ #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_TASKS_STOP */ /* Description: Task stopping the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the random number generator */ #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_EVENTS_VALRDY */ /* Description: Event being generated for every new random number written to the VALUE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new random number written to the VALUE register */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ /* Register: RNG_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between VALRDY event and STOP task */ +/* Bit 0 : Shortcut between event VALRDY and task STOP */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -11042,7 +11303,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11052,7 +11313,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11082,91 +11343,101 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_TASKS_START */ /* Description: Start RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Start RTC COUNTER */ #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_STOP */ /* Description: Stop RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Stop RTC COUNTER */ #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_CLEAR */ /* Description: Clear RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Clear RTC COUNTER */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_TRIGOVRFLW */ /* Description: Set COUNTER to 0xFFFFF0 */ -/* Bit 0 : */ +/* Bit 0 : Set COUNTER to 0xFFFFF0 */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_EVENTS_TICK */ /* Description: Event on COUNTER increment */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER increment */ #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_OVRFLW */ /* Description: Event on COUNTER overflow */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER overflow */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: RTC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TICK event */ +/* Bit 0 : Write '1' to enable interrupt for event TICK */ #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11176,42 +11447,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TICK event */ +/* Bit 0 : Write '1' to disable interrupt for event TICK */ #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11221,81 +11492,81 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTEN */ /* Description: Enable or disable event routing */ -/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ -/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ -/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ -/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ -/* Bit 1 : Enable or disable event routing for OVRFLW event */ +/* Bit 1 : Enable or disable event routing for event OVRFLW */ #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ -/* Bit 0 : Enable or disable event routing for TICK event */ +/* Bit 0 : Enable or disable event routing for event TICK */ #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ -/* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable event routing for TICK event */ +/* Bit 0 : Write '1' to enable event routing for event TICK */ #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11305,42 +11576,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTENCLR */ /* Description: Disable event routing */ -/* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable event routing for TICK event */ +/* Bit 0 : Write '1' to disable event routing for event TICK */ #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11362,7 +11633,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: RTC_CC */ -/* Description: Description collection[n]: Compare register n */ +/* Description: Description collection: Compare register n */ /* Bits 23..0 : Compare value */ #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ @@ -11375,217 +11646,237 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_TASKS_START */ /* Description: Starts the SAADC and prepares the result buffer in RAM */ -/* Bit 0 : */ +/* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */ #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_SAMPLE */ /* Description: Takes one SAADC sample */ -/* Bit 0 : */ +/* Bit 0 : Takes one SAADC sample */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_STOP */ /* Description: Stops the SAADC and terminates all on-going conversions */ -/* Bit 0 : */ +/* Bit 0 : Stops the SAADC and terminates all on-going conversions */ #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_CALIBRATEOFFSET */ /* Description: Starts offset auto-calibration */ -/* Bit 0 : */ +/* Bit 0 : Starts offset auto-calibration */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_EVENTS_STARTED */ /* Description: The SAADC has started */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has started */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_END */ /* Description: The SAADC has filled up the result buffer */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has filled up the result buffer */ #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_DONE */ /* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ -/* Bit 0 : */ +/* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_RESULTDONE */ /* Description: Result ready for transfer to RAM */ -/* Bit 0 : */ +/* Bit 0 : Result ready for transfer to RAM */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CALIBRATEDONE */ /* Description: Calibration is complete */ -/* Bit 0 : */ +/* Bit 0 : Calibration is complete */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_STOPPED */ /* Description: The SAADC has stopped */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has stopped */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITH */ -/* Description: Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */ +/* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */ -/* Bit 0 : */ +/* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITL */ -/* Description: Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */ +/* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */ -/* Bit 0 : */ +/* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ /* Register: SAADC_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for STOPPED event */ +/* Bit 5 : Enable or disable interrupt for event STOPPED */ #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for DONE event */ +/* Bit 2 : Enable or disable interrupt for event DONE */ #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for END event */ +/* Bit 1 : Enable or disable interrupt for event END */ #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -11594,154 +11885,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for DONE event */ +/* Bit 2 : Write '1' to enable interrupt for event DONE */ #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11751,154 +12042,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for DONE event */ +/* Bit 2 : Write '1' to disable interrupt for event DONE */ #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11924,7 +12215,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */ /* Register: SAADC_CH_PSELP */ -/* Description: Description cluster[n]: Input positive pin selection for CH[n] */ +/* Description: Description cluster: Input positive pin selection for CH[n] */ /* Bits 4..0 : Analog positive input channel */ #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ @@ -11942,7 +12233,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_PSELN */ -/* Description: Description cluster[n]: Input negative pin selection for CH[n] */ +/* Description: Description cluster: Input negative pin selection for CH[n] */ /* Bits 4..0 : Analog negative input, enables differential channel */ #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ @@ -11960,7 +12251,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_CONFIG */ -/* Description: Description cluster[n]: Input configuration for CH[n] */ +/* Description: Description cluster: Input configuration for CH[n] */ /* Bit 24 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ @@ -12019,7 +12310,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ /* Register: SAADC_CH_LIMIT */ -/* Description: Description cluster[n]: High/low limits for event monitoring of a channel */ +/* Description: Description cluster: High/low limits for event monitoring of a channel */ /* Bits 31..16 : High level limit */ #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ @@ -12097,14 +12388,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_EVENTS_READY */ /* Description: TXD byte sent and RXD byte received */ -/* Bit 0 : */ +/* Bit 0 : TXD byte sent and RXD byte received */ #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: SPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for READY event */ +/* Bit 2 : Write '1' to enable interrupt for event READY */ #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12114,7 +12407,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for READY event */ +/* Bit 2 : Write '1' to disable interrupt for event READY */ #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12237,70 +12530,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_TASKS_START */ /* Description: Start SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Start SPI transaction */ #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_STOP */ /* Description: Stop SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop SPI transaction */ #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_SUSPEND */ /* Description: Suspend SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend SPI transaction */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_RESUME */ /* Description: Resume SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume SPI transaction */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_EVENTS_STOPPED */ /* Description: SPI transaction has stopped */ -/* Bit 0 : */ +/* Bit 0 : SPI transaction has stopped */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_END */ /* Description: End of RXD buffer and TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer and TXD buffer reached */ #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDTX */ /* Description: End of TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of TXD buffer reached */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_STARTED */ /* Description: Transaction started */ -/* Bit 0 : */ +/* Bit 0 : Transaction started */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 17 : Shortcut between END event and START task */ +/* Bit 17 : Shortcut between event END and task START */ #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ @@ -12309,35 +12616,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for STARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for END event */ +/* Bit 6 : Write '1' to enable interrupt for event END */ #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12347,35 +12654,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for STARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for END event */ +/* Bit 6 : Write '1' to disable interrupt for event END */ #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12632,42 +12939,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_TASKS_ACQUIRE */ /* Description: Acquire SPI semaphore */ -/* Bit 0 : */ +/* Bit 0 : Acquire SPI semaphore */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_TASKS_RELEASE */ /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ -/* Bit 0 : */ +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_EVENTS_END */ /* Description: Granted transaction completed */ -/* Bit 0 : */ +/* Bit 0 : Granted transaction completed */ #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ACQUIRED */ /* Description: Semaphore acquired */ -/* Bit 0 : */ +/* Bit 0 : Semaphore acquired */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ /* Register: SPIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 2 : Shortcut between END event and ACQUIRE task */ +/* Bit 2 : Shortcut between event END and task ACQUIRE */ #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ @@ -12676,21 +12991,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12700,21 +13015,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12847,6 +13162,15 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_TXD_PTR */ /* Description: TXD data pointer */ @@ -12868,6 +13192,15 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_CONFIG */ /* Description: Configuration register */ @@ -12910,28 +13243,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_TASKS_START */ /* Description: Start temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Start temperature measurement */ #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_TASKS_STOP */ /* Description: Stop temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop temperature measurement */ #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_EVENTS_DATARDY */ /* Description: Temperature measurement complete, data ready */ -/* Bit 0 : */ +/* Bit 0 : Temperature measurement complete, data ready */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ /* Register: TEMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -12941,7 +13278,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -13081,122 +13418,130 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_TASKS_START */ /* Description: Start Timer */ -/* Bit 0 : */ +/* Bit 0 : Start Timer */ #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_STOP */ /* Description: Stop Timer */ -/* Bit 0 : */ +/* Bit 0 : Stop Timer */ #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_COUNT */ /* Description: Increment Timer (Counter mode only) */ -/* Bit 0 : */ +/* Bit 0 : Increment Timer (Counter mode only) */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CLEAR */ /* Description: Clear time */ -/* Bit 0 : */ +/* Bit 0 : Clear time */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_SHUTDOWN */ /* Description: Deprecated register - Shut down timer */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - Shut down timer */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CAPTURE */ -/* Description: Description collection[n]: Capture Timer value to CC[n] register */ +/* Description: Description collection: Capture Timer value to CC[n] register */ -/* Bit 0 : */ +/* Bit 0 : Capture Timer value to CC[n] register */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: TIMER_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ @@ -13205,42 +13550,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13250,42 +13595,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13321,7 +13666,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: TIMER_CC */ -/* Description: Description collection[n]: Capture/Compare register n */ +/* Description: Description collection: Capture/Compare register n */ /* Bits 31..0 : Capture/Compare value */ #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ @@ -13334,90 +13679,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_TASKS_STARTRX */ /* Description: Start TWI receive sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI receive sequence */ #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI transmit sequence */ #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_STOP */ /* Description: Stop TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction */ #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_RXDREADY */ /* Description: TWI RXD byte received */ -/* Bit 0 : */ +/* Bit 0 : TWI RXD byte received */ #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_TXDSENT */ /* Description: TWI TXD byte sent */ -/* Bit 0 : */ +/* Bit 0 : TWI TXD byte sent */ #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_BB */ /* Description: TWI byte boundary, generated before each byte that is sent or received */ -/* Bit 0 : */ +/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_SUSPENDED */ /* Description: TWI entered the suspended state */ -/* Bit 0 : */ +/* Bit 0 : TWI entered the suspended state */ #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ /* Register: TWI_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 1 : Shortcut between BB event and STOP task */ +/* Bit 1 : Shortcut between event BB and task STOP */ #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between BB event and SUSPEND task */ +/* Bit 0 : Shortcut between event BB and task SUSPEND */ #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -13426,42 +13788,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for BB event */ +/* Bit 14 : Write '1' to enable interrupt for event BB */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13471,42 +13833,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for BB event */ +/* Bit 14 : Write '1' to disable interrupt for event BB */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13615,121 +13977,140 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_TASKS_STARTRX */ /* Description: Start TWI receive sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI receive sequence */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI transmit sequence */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STOP */ /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : */ +/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTRX */ /* Description: Byte boundary, starting to receive the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to receive the last byte */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTTX */ /* Description: Byte boundary, starting to transmit the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to transmit the last byte */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 12 : Shortcut between LASTRX event and STOP task */ +/* Bit 12 : Shortcut between event LASTRX and task STOP */ #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between LASTRX event and SUSPEND task */ +/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between LASTTX event and STOP task */ +/* Bit 9 : Shortcut between event LASTTX and task STOP */ #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -13738,43 +14119,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for LASTTX event */ +/* Bit 24 : Enable or disable interrupt for event LASTTX */ #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for LASTRX event */ +/* Bit 23 : Enable or disable interrupt for event LASTRX */ #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -13783,49 +14164,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13835,49 +14216,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14032,90 +14413,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_TASKS_STOP */ /* Description: Stop TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction */ #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARERX */ /* Description: Prepare the TWI slave to respond to a write command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a write command */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARETX */ /* Description: Prepare the TWI slave to respond to a read command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a read command */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_WRITE */ /* Description: Write command received */ -/* Bit 0 : */ +/* Bit 0 : Write command received */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_READ */ /* Description: Read command received */ -/* Bit 0 : */ +/* Bit 0 : Read command received */ #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ /* Register: TWIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 14 : Shortcut between READ event and SUSPEND task */ +/* Bit 14 : Shortcut between event READ and task SUSPEND */ #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -14124,37 +14522,37 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 26 : Enable or disable interrupt for READ event */ +/* Bit 26 : Enable or disable interrupt for event READ */ #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for WRITE event */ +/* Bit 25 : Enable or disable interrupt for event WRITE */ #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -14163,42 +14561,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 26 : Write '1' to enable interrupt for READ event */ +/* Bit 26 : Write '1' to enable interrupt for event READ */ #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for WRITE event */ +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14208,42 +14606,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 26 : Write '1' to disable interrupt for READ event */ +/* Bit 26 : Write '1' to disable interrupt for event READ */ #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for WRITE event */ +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14342,6 +14740,15 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_TXD_PTR */ /* Description: TXD Data pointer */ @@ -14363,8 +14770,17 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_ADDRESS */ -/* Description: Description collection[n]: TWI slave address n */ +/* Description: Description collection: TWI slave address n */ /* Bits 6..0 : TWI slave address */ #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ @@ -14399,90 +14815,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_TASKS_STARTRX */ /* Description: Start UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Start UART receiver */ #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STOPRX */ /* Description: Stop UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Stop UART receiver */ #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STARTTX */ /* Description: Start UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Start UART transmitter */ #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STOPTX */ /* Description: Stop UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Stop UART transmitter */ #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_SUSPEND */ /* Description: Suspend UART */ -/* Bit 0 : */ +/* Bit 0 : Suspend UART */ #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: UART_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_RXDRDY */ /* Description: Data received in RXD */ -/* Bit 0 : */ +/* Bit 0 : Data received in RXD */ #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ -/* Bit 0 : */ +/* Bit 0 : Data sent from TXD */ #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_ERROR */ /* Description: Error detected */ -/* Bit 0 : */ +/* Bit 0 : Error detected */ #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_RXTO */ /* Description: Receiver timeout */ -/* Bit 0 : */ +/* Bit 0 : Receiver timeout */ #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ /* Register: UART_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +/* Bit 4 : Shortcut between event NCTS and task STOPRX */ #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between CTS event and STARTRX task */ +/* Bit 3 : Shortcut between event CTS and task STARTRX */ #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14491,42 +14924,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENSET */ /* Description: Enable interrupt */ -/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14536,42 +14969,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14724,6 +15157,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_CONFIG */ /* Description: Configuration of parity and hardware flow control */ +/* Bit 4 : Stop bits */ +#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + /* Bits 3..1 : Parity */ #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ @@ -14743,125 +15182,152 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_TASKS_STARTRX */ /* Description: Start UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Start UART receiver */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPRX */ /* Description: Stop UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Stop UART receiver */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STARTTX */ /* Description: Start UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Start UART transmitter */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPTX */ /* Description: Stop UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Stop UART transmitter */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_FLUSHRX */ /* Description: Flush RX FIFO into RX buffer */ -/* Bit 0 : */ +/* Bit 0 : Flush RX FIFO into RX buffer */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXDRDY */ /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ -/* Bit 0 : */ +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDRX */ /* Description: Receive buffer is filled up */ -/* Bit 0 : */ +/* Bit 0 : Receive buffer is filled up */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ -/* Bit 0 : */ +/* Bit 0 : Data sent from TXD */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDTX */ /* Description: Last TX byte transmitted */ -/* Bit 0 : */ +/* Bit 0 : Last TX byte transmitted */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ERROR */ /* Description: Error detected */ -/* Bit 0 : */ +/* Bit 0 : Error detected */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXTO */ /* Description: Receiver timeout */ -/* Bit 0 : */ +/* Bit 0 : Receiver timeout */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXSTARTED */ /* Description: UART receiver has started */ -/* Bit 0 : */ +/* Bit 0 : UART receiver has started */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTARTED */ /* Description: UART transmitter has started */ -/* Bit 0 : */ +/* Bit 0 : UART transmitter has started */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTOPPED */ /* Description: Transmitter stopped */ -/* Bit 0 : */ +/* Bit 0 : Transmitter stopped */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14870,67 +15336,67 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for RXTO event */ +/* Bit 17 : Enable or disable interrupt for event RXTO */ #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for ENDTX event */ +/* Bit 8 : Enable or disable interrupt for event ENDTX */ #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for ENDRX event */ +/* Bit 4 : Enable or disable interrupt for event ENDRX */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for NCTS event */ +/* Bit 1 : Enable or disable interrupt for event NCTS */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for CTS event */ +/* Bit 0 : Enable or disable interrupt for event CTS */ #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ @@ -14939,77 +15405,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15019,77 +15485,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15293,28 +15759,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: User information configuration registers */ /* Register: UICR_NRFFW */ -/* Description: Description collection[n]: Reserved for Nordic firmware design */ +/* Description: Description collection: Reserved for Nordic firmware design */ /* Bits 31..0 : Reserved for Nordic firmware design */ #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ /* Register: UICR_NRFHW */ -/* Description: Description collection[n]: Reserved for Nordic hardware design */ +/* Description: Description collection: Reserved for Nordic hardware design */ /* Bits 31..0 : Reserved for Nordic hardware design */ #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ /* Register: UICR_CUSTOMER */ -/* Description: Description collection[n]: Reserved for customer */ +/* Description: Description collection: Reserved for customer */ /* Bits 31..0 : Reserved for customer */ #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ /* Register: UICR_PSELRESET */ -/* Description: Description collection[n]: Mapping of the nRESET function */ +/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ /* Bit 31 : Connection */ #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -15326,7 +15792,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */ #define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ -/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */ +/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ @@ -15364,9 +15830,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ /* Register: UICR_REGOUT0 */ -/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ +/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */ -/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ +/* Bits 2..0 : Output voltage from REG0 regulator stage. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ #define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ @@ -15382,173 +15848,204 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Universal serial bus device */ /* Register: USBD_TASKS_STARTEPIN */ -/* Description: Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ +/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ -/* Bit 0 : */ +/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTISOIN */ /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ -/* Bit 0 : */ +/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTEPOUT */ -/* Description: Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ +/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ -/* Bit 0 : */ +/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTISOOUT */ /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ -/* Bit 0 : */ +/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0RCVOUT */ /* Description: Allows OUT data stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Allows OUT data stage on control endpoint 0 */ #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */ #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0STATUS */ /* Description: Allows status stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Allows status stage on control endpoint 0 */ #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */ #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0STALL */ /* Description: Stalls data and status stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Stalls data and status stage on control endpoint 0 */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_DPDMDRIVE */ /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ -/* Bit 0 : */ +/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_DPDMNODRIVE */ /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ -/* Bit 0 : */ +/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_EVENTS_USBRESET */ /* Description: Signals that a USB reset condition has been detected on USB lines */ -/* Bit 0 : */ +/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */ #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_STARTED */ /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ -/* Bit 0 : */ +/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPIN */ -/* Description: Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EP0DATADONE */ /* Description: An acknowledged data transfer has taken place on the control endpoint */ -/* Bit 0 : */ +/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */ #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */ #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOIN */ -/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPOUT */ -/* Description: Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOOUT */ -/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_SOF */ /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ -/* Bit 0 : */ +/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */ #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_USBEVENT */ /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ -/* Bit 0 : */ +/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EP0SETUP */ /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */ -/* Bit 0 : */ +/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */ #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */ #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EPDATA */ /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ -/* Bit 0 : */ +/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */ #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */ /* Register: USBD_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ +/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */ +/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */ +/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */ +/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */ +/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ @@ -15557,151 +16054,151 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for EPDATA event */ +/* Bit 24 : Enable or disable interrupt for event EPDATA */ #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for EP0SETUP event */ +/* Bit 23 : Enable or disable interrupt for event EP0SETUP */ #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ -/* Bit 22 : Enable or disable interrupt for USBEVENT event */ +/* Bit 22 : Enable or disable interrupt for event USBEVENT */ #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ -/* Bit 21 : Enable or disable interrupt for SOF event */ +/* Bit 21 : Enable or disable interrupt for event SOF */ #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */ +/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */ #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */ #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */ #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */ #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */ #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */ #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */ #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */ #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */ #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for ENDISOIN event */ +/* Bit 11 : Enable or disable interrupt for event ENDISOIN */ #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */ +/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */ #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */ #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */ #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */ #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */ #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */ #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */ #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */ #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */ #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STARTED event */ +/* Bit 1 : Enable or disable interrupt for event STARTED */ #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for USBRESET event */ +/* Bit 0 : Enable or disable interrupt for event USBRESET */ #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ @@ -15710,175 +16207,175 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to enable interrupt for event EPDATA */ #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */ #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */ #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for SOF event */ +/* Bit 21 : Write '1' to enable interrupt for event SOF */ #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */ #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */ #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */ #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */ #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */ #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */ #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */ #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */ #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */ #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */ #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */ #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */ #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */ #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */ #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */ #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */ #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */ #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */ #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */ #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STARTED event */ +/* Bit 1 : Write '1' to enable interrupt for event STARTED */ #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to enable interrupt for event USBRESET */ #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -15888,175 +16385,175 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to disable interrupt for event EPDATA */ #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */ #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */ #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for SOF event */ +/* Bit 21 : Write '1' to disable interrupt for event SOF */ #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */ #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */ #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */ #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */ #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */ #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */ #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */ #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */ #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */ #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */ #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */ #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */ #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */ #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */ #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */ #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */ #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */ #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */ #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */ #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STARTED event */ +/* Bit 1 : Write '1' to disable interrupt for event STARTED */ #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to disable interrupt for event USBRESET */ #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -16097,7 +16594,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ /* Register: USBD_HALTED_EPIN */ -/* Description: Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16106,7 +16603,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ /* Register: USBD_HALTED_EPOUT */ -/* Description: Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16404,7 +16901,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ /* Register: USBD_SIZE_EPOUT */ -/* Description: Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint */ +/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */ /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ @@ -16639,21 +17136,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ /* Register: USBD_EPIN_PTR */ -/* Description: Description cluster[n]: Data pointer */ +/* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPIN_MAXCNT */ -/* Description: Description cluster[n]: Maximum number of bytes to transfer */ +/* Description: Description cluster: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPIN_AMOUNT */ -/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16662,7 +17159,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOIN_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -16681,21 +17178,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: USBD_EPOUT_PTR */ -/* Description: Description cluster[n]: Data pointer */ +/* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPOUT_MAXCNT */ -/* Description: Description cluster[n]: Maximum number of bytes to transfer */ +/* Description: Description cluster: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPOUT_AMOUNT */ -/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16704,7 +17201,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOOUT_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -16729,21 +17226,24 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_TASKS_START */ /* Description: Start the watchdog */ -/* Bit 0 : */ +/* Bit 0 : Start the watchdog */ #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: WDT_EVENTS_TIMEOUT */ /* Description: Watchdog timeout */ -/* Bit 0 : */ +/* Bit 0 : Watchdog timeout */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ /* Register: WDT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16753,7 +17253,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16894,7 +17394,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ /* Register: WDT_RR */ -/* Description: Description collection[n]: Reload request n */ +/* Description: Description collection: Reload request n */ /* Bits 31..0 : Reload request register */ #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ diff --git a/cpu/nrf52/include/vendor/nrf52_bitfields.h b/cpu/nrf52/include/vendor/nrf52_bitfields.h index 2b4aa81048..93939c14ec 100644 --- a/cpu/nrf52/include/vendor/nrf52_bitfields.h +++ b/cpu/nrf52/include/vendor/nrf52_bitfields.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: