boards/nucleo-l4r5zi: adapt to new generic clock config
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@ -20,6 +20,19 @@
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#define PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "periph_cpu.h"
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/* Add specific clock configuration (HSE, LSE) for this board here */
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#define CLOCK_CORECLOCK_MAX MHZ(120)
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (30)
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#endif
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#include "l4/cfg_clock_default.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_rtt_default.h"
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#include "cfg_rtt_default.h"
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@ -27,47 +40,6 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (0)
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#ifndef CLOCK_LSE
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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#endif
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/* 0: enable MSI only if HSE isn't available
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* 1: always enable MSI (e.g. if USB or RNG is used)*/
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#define CLOCK_MSI_ENABLE (1)
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#ifndef CLOCK_MSI_LSE_PLL
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/* 0: disable Hardware auto calibration with LSE
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* 1: enable Hardware auto calibration with LSE (PLL-mode)
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* Same as with CLOCK_LSE above this defaults to 0 because LSE is
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* mandatory for MSI/LSE-trimming to work */
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#define CLOCK_MSI_LSE_PLL (0)
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#endif
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/* give the target core clock (HCLK) frequency [in Hz], maximum: 120MHz */
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#define CLOCK_CORECLOCK (120000000U)
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/* PLL configuration: make sure your values are legit! */
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (30)
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#define CLOCK_PLL_R (2)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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/**
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* @name Timer configuration
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* @name Timer configuration
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* @{
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* @{
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