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cpu/cc2538: cleanup periph timer implementation

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Refine periph timer implementation to use vendor header defines
    where possible, remove unnecessary structs and general cleanup.
This commit is contained in:
smlng 2018-08-03 09:36:50 +02:00
parent 3e7c5423e5
commit b7ab6b4b36
1 changed files with 19 additions and 30 deletions
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43
cpu/cc2538/periph/timer.c
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@ -22,6 +22,9 @@
#include <assert.h> #include <assert.h>
#include <stdint.h> #include <stdint.h>
#include "vendor/hw_gptimer.h"
#include "vendor/hw_memmap.h"
#include "board.h" #include "board.h"
#include "cpu.h" #include "cpu.h"
#include "periph/timer.h" #include "periph/timer.h"
@ -35,19 +38,13 @@
#define TIMER_A_IRQ_MASK (0x000000ff) #define TIMER_A_IRQ_MASK (0x000000ff)
#define TIMER_B_IRQ_MASK (0x0000ff00) #define TIMER_B_IRQ_MASK (0x0000ff00)
#define BIT(n) ( 1UL << (n) ) /* GPTIMER_CTL Bits */
#define TBEN GPTIMER_CTL_TBEN
#define TAEN GPTIMER_CTL_TAEN
/* GPTIMER_CTL Bits: */ /* GPTIMER_TnMR Bits */
#define TBEN BIT(8) #define TNMIE GPTIMER_TAMR_TAMIE
#define TAEN BIT(0) #define TNCDIR GPTIMER_TAMR_TACDIR
/* GPTIMER_TnMR Bits: */
#define TnCMIE BIT(5)
#define TnCDIR BIT(4)
/* GPTIMER_IMR Bits: */
#define TBMIM BIT(11)
#define TAMIM BIT(4)
typedef struct { typedef struct {
uint16_t mask; uint16_t mask;
@ -55,15 +52,8 @@ typedef struct {
} _isr_cfg_t; } _isr_cfg_t;
static const _isr_cfg_t chn_isr_cfg[] = { static const _isr_cfg_t chn_isr_cfg[] = {
{ .mask = TIMER_A_IRQ_MASK, .flag = TAMIM }, { .mask = TIMER_A_IRQ_MASK, .flag = GPTIMER_IMR_TAMIM },
{ .mask = TIMER_B_IRQ_MASK, .flag = TBMIM } { .mask = TIMER_B_IRQ_MASK, .flag = GPTIMER_IMR_TBMIM }
};
static const int irqn_cfg[] = {
GPTIMER_0A_IRQn,
GPTIMER_1A_IRQn,
GPTIMER_2A_IRQn,
GPTIMER_3A_IRQn
}; };
/** /**
@ -77,7 +67,7 @@ static inline void _irq_enable(tim_t tim)
DEBUG("%s(%u)\n", __FUNCTION__, tim); DEBUG("%s(%u)\n", __FUNCTION__, tim);
if (tim < TIMER_NUMOF) { if (tim < TIMER_NUMOF) {
IRQn_Type irqn = irqn_cfg[tim]; IRQn_Type irqn = GPTIMER_0A_IRQn + (2 * tim);
NVIC_SetPriority(irqn, TIMER_IRQ_PRIO); NVIC_SetPriority(irqn, TIMER_IRQ_PRIO);
NVIC_EnableIRQ(irqn); NVIC_EnableIRQ(irqn);
@ -94,7 +84,7 @@ static inline cc2538_gptimer_t *dev(tim_t tim)
{ {
assert(tim < TIMER_NUMOF); assert(tim < TIMER_NUMOF);
return ((cc2538_gptimer_t *)(GPTIMER_BASE | (((uint32_t)tim) << 12))); return ((cc2538_gptimer_t *)(GPTIMER0_BASE | (((uint32_t)tim) << 12)));
} }
/** /**
@ -110,21 +100,20 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
} }
/* Save the callback function: */ /* Save the callback function: */
assert(tim < TIMER_NUMOF);
isr_ctx[tim].cb = cb; isr_ctx[tim].cb = cb;
isr_ctx[tim].arg = arg; isr_ctx[tim].arg = arg;
/* Enable the clock for this timer: */ /* Enable the clock for this timer: */
SYS_CTRL_RCGCGPT |= (1 << tim); SYS_CTRL->RCGCGPT |= (1 << tim);
/* Disable this timer before configuring it: */ /* Disable this timer before configuring it: */
dev(tim)->cc2538_gptimer_ctl.CTL = 0; dev(tim)->cc2538_gptimer_ctl.CTL = 0;
uint32_t prescaler = 0; uint32_t prescaler = 0;
uint32_t chan_mode = TnCMIE | GPTIMER_PERIODIC_MODE; uint32_t chan_mode = TNMIE | GPTIMER_PERIODIC_MODE;
if (timer_config[tim].cfg == GPTMCFG_32_BIT_TIMER) { if (timer_config[tim].cfg == GPTMCFG_32_BIT_TIMER) {
/* Count up in periodic mode */ /* Count up in periodic mode */
chan_mode |= TnCDIR ; chan_mode |= TNCDIR ;
if (timer_config[tim].chn > 1) { if (timer_config[tim].chn > 1) {
DEBUG("Invalid timer_config. Multiple channels are available only in 16-bit mode."); DEBUG("Invalid timer_config. Multiple channels are available only in 16-bit mode.");