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cpu/lpc11u34: adapted to PWM interface changes

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This commit is contained in:
Hauke Petersen 2015-10-21 12:42:52 +02:00 committed by Joakim Nohlgård
parent eff628ad9b
commit b96cb04df2
1 changed files with 42 additions and 28 deletions
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70
cpu/lpc11u34/periph/pwm.c
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@ -20,28 +20,28 @@
#include "bitarithm.h"
#include "periph/gpio.h"
#include "periph/pwm.h"
#include "board.h"
#include "periph_conf.h"
/* guard file in case no PWM device is defined */
#include "periph/pwm.h"
#if (PWM_0_EN || PWM_1_EN)
/**
* @note The LPC11U34 doesn't support centerized alignements
*/
int pwm_init(pwm_t dev, pwm_mode_t mode, unsigned int frequency, unsigned int resolution)
uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
{
switch (dev) {
#if PWM_0_EN
case PWM_0:
/* This CPU doesn't support a centerized alignement */
if (mode == PWM_CENTER) {
return -1;
return 0;
}
/* Check if the frequency and resolution is applicable */
if (CLOCK_CORECLOCK/(resolution*frequency) <= 0) {
return -2;
if (CLOCK_CORECLOCK / (res * freq) <= 0) {
return 0;
}
#if PWM_0_CH0_EN
PWM_0_CH0_IOCON = (PWM_0_CH0_IOCON & ~(BIT7 | 7)) | PWM_0_CH0_AF;
@ -57,20 +57,20 @@ int pwm_init(pwm_t dev, pwm_mode_t mode, unsigned int frequency, unsigned int re
/* Enable timer and keep it in reset state */
PWM_0_DEV->TCR = BIT0 | BIT1;
/* Set the prescaler (CLOCK_CORECLOCK / resolution) */
PWM_0_DEV->PR = (CLOCK_CORECLOCK/(resolution*frequency));
PWM_0_DEV->PR = (CLOCK_CORECLOCK / (res * freq));
/* Reset timer on MR3 */
PWM_0_DEV->MCR = BIT10;
/* Set PWM period */
PWM_0_DEV->MR0 = (resolution);
PWM_0_DEV->MR1 = (resolution);
PWM_0_DEV->MR2 = (resolution);
PWM_0_DEV->MR3 = (resolution)-1;
PWM_0_DEV->MR0 = res;
PWM_0_DEV->MR1 = res;
PWM_0_DEV->MR2 = res;
PWM_0_DEV->MR3 = res - 1;
/* Set mode for channels 0..2 */
PWM_0_DEV->EMR |= ((mode+1) << 4);
PWM_0_DEV->EMR |= ((mode+1) << 6);
PWM_0_DEV->EMR |= ((mode+1) << 8);
PWM_0_DEV->EMR |= ((mode + 1) << 4);
PWM_0_DEV->EMR |= ((mode + 1) << 6);
PWM_0_DEV->EMR |= ((mode + 1) << 8);
/* Enable PWM channels 0..2 */
PWM_0_DEV->PWMC = BIT0 | BIT1 | BIT2;
@ -79,11 +79,11 @@ int pwm_init(pwm_t dev, pwm_mode_t mode, unsigned int frequency, unsigned int re
case PWM_1:
/* This CPU doesn't support a centerized alignement */
if (mode == PWM_CENTER) {
return -1;
return 0;
}
/* Check if the frequency and resolution is applicable */
if (CLOCK_CORECLOCK/(resolution*frequency) <= 0) {
return -2;
if (CLOCK_CORECLOCK / (res * freq) <= 0) {
return 0;
}
#if PWM_1_CH0_EN
PWM_1_CH0_IOCON = (PWM_1_CH0_IOCON & ~(BIT7 | 7)) | PWM_1_CH0_AF;
@ -99,30 +99,46 @@ int pwm_init(pwm_t dev, pwm_mode_t mode, unsigned int frequency, unsigned int re
/* Enable timer and keep it in reset state */
PWM_1_DEV->TCR = BIT0 | BIT1;
/* Set the prescaler (CLOCK_CORECLOCK / resolution) */
PWM_1_DEV->PR = (CLOCK_CORECLOCK/(resolution*frequency));
PWM_1_DEV->PR = (CLOCK_CORECLOCK / (res * freq));
/* Reset timer on MR3 */
PWM_1_DEV->MCR = BIT10;
/* Set PWM period */
PWM_1_DEV->MR0 = (resolution);
PWM_1_DEV->MR1 = (resolution);
PWM_1_DEV->MR2 = (resolution);
PWM_1_DEV->MR3 = (resolution)-1;
PWM_1_DEV->MR0 = res;
PWM_1_DEV->MR1 = res;
PWM_1_DEV->MR2 = res;
PWM_1_DEV->MR3 = res - 1;
/* Set mode for channels 0..2 */
PWM_1_DEV->EMR |= ((mode+1) << 4);
PWM_1_DEV->EMR |= ((mode+1) << 6);
PWM_1_DEV->EMR |= ((mode+1) << 8);
PWM_1_DEV->EMR |= ((mode + 1) << 4);
PWM_1_DEV->EMR |= ((mode + 1) << 6);
PWM_1_DEV->EMR |= ((mode + 1) << 8);
/* Enable PWM channels 0..2 */
PWM_1_DEV->PWMC = BIT0 | BIT1 | BIT2;
#endif /* PWM_1_EN */
}
return frequency;
return freq;
}
int pwm_set(pwm_t dev, int channel, unsigned int value)
uint8_t pwm_channels(pwm_t dev)
{
switch (dev) {
#if PWM_0_EN
case PWM_0:
return PWM_0_CHANNELS;
#endif
#if PWM_1_EN
case PWM_1:
return PWM_1_CHANNELS;
#endif
default:
return 0;
}
}
void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
{
switch (dev) {
#if PWM_0_EN
@ -140,8 +156,6 @@ int pwm_set(pwm_t dev, int channel, unsigned int value)
break;
#endif
}
return 0;
}
void pwm_start(pwm_t dev)