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cortexm_common: don't try to set MEMFAULTENA on ARMv6-M

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Before this change, if one tried to build a Cortex-M0+ target that had
an MPU, compilation would fail due to missing
'SCB_SHCSR_MEMFAULTENA_Msk' in SCB structure. Cortex-M0+ is a ARMv6-M
arch (unlike most other targets that have MPU support). ARMv6-M has more
limited support for fault conditions, see ARMv6-M Architecture Reference
Manual, D3.6.2.
This commit is contained in:
Girts Folkmanis 2018-03-02 21:20:21 -08:00
parent 51febf097e
commit b9744f698f
1 changed files with 6 additions and 1 deletions
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7
cpu/cortexm_common/mpu.c
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@ -36,8 +36,13 @@ int mpu_enable(void) {
#if __MPU_PRESENT #if __MPU_PRESENT
MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk; MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
/* Enable the memory fault exception */ #ifdef SCB_SHCSR_MEMFAULTENA_Msk
/* Enable the memory fault exception if SCB SHCSR (System Handler Control
* and State Register) has a separate bit for mem faults. That is the case
* on ARMv7-M. ARMv6-M does not support separate exception enable for mem
* faults and all fault conditions cause a HardFault. */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
return 0; return 0;
#else #else