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cpu, cc2538: adapt uart to RIOT gpio API

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This commit is contained in:
smlng 2017-07-04 11:41:16 +02:00
parent ef3c6022f2
commit ba324ef07c
1 changed files with 9 additions and 42 deletions
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51
cpu/cc2538/periph/uart.c
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@ -1,5 +1,6 @@
/* /*
* Copyright (C) 2014 Loci Controls Inc. * Copyright (C) 2014 Loci Controls Inc.
* 2017 HAW Hamburg
* *
* This file is subject to the terms and conditions of the GNU Lesser * This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level * General Public License v2.1. See the file LICENSE in the top level
@ -15,7 +16,7 @@
* @brief Low-level UART driver implementation * @brief Low-level UART driver implementation
* *
* @author Ian Martin <ian@locicontrols.com> * @author Ian Martin <ian@locicontrols.com>
* * @author Sebastian Meiling <s@mlng.net>
* @} * @}
*/ */
@ -192,45 +193,15 @@ static int init_base(uart_t uart, uint32_t baudrate)
#if UART_0_EN #if UART_0_EN
case UART_0: case UART_0:
u = UART_0_DEV; u = UART_0_DEV;
gpio_init_af(UART_0_RX_PIN, UART0_RXD, GPIO_IN);
/* gpio_init_af(UART_0_TX_PIN, UART0_TXD, GPIO_OUT);
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*/
IOC_UARTRXD_UART0 = UART_0_RX_PIN;
/*
* Pad Control for the TX pin:
* - Set function to UARTn TX
* - Output Enable
*/
IOC_PXX_SEL[UART_0_TX_PIN] = UART0_TXD;
IOC_PXX_OVER[UART_0_TX_PIN] = IOC_OVERRIDE_OE;
/* Set RX and TX pins to peripheral mode */
gpio_hardware_control(UART_0_TX_PIN);
gpio_hardware_control(UART_0_RX_PIN);
break; break;
#endif #endif
#if UART_1_EN #if UART_1_EN
case UART_1: case UART_1:
u = UART_1_DEV; u = UART_1_DEV;
gpio_init_af(UART_1_RX_PIN, UART1_RXD, GPIO_IN);
/* gpio_init_af(UART_1_TX_PIN, UART1_TXD, GPIO_OUT);
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
*/
IOC_UARTRXD_UART1 = UART_1_RX_PIN;
/*
* Pad Control for the TX pin:
* - Set function to UARTn TX
* - Output Enable
*/
IOC_PXX_SEL[UART_1_TX_PIN] = UART1_TXD;
IOC_PXX_OVER[UART_1_TX_PIN] = IOC_OVERRIDE_OE;
/* Set RX and TX pins to peripheral mode */
gpio_hardware_control(UART_1_TX_PIN);
gpio_hardware_control(UART_1_RX_PIN);
break; break;
#endif #endif
@ -255,16 +226,12 @@ static int init_base(uart_t uart, uint32_t baudrate)
/* On the CC2538, hardware flow control is supported only on UART1 */ /* On the CC2538, hardware flow control is supported only on UART1 */
if (u == UART1) { if (u == UART1) {
#ifdef UART_1_RTS_PIN #ifdef UART_1_RTS_PIN
IOC_PXX_SEL[UART_1_RTS_PIN] = UART1_RTS; gpio_init_af(UART_1_RTS_PIN, UART1_RTS, GPIO_OUT);
gpio_hardware_control(UART_1_RTS_PIN);
IOC_PXX_OVER[UART_1_RTS_PIN] = IOC_OVERRIDE_OE;
u->cc2538_uart_ctl.CTLbits.RTSEN = 1; u->cc2538_uart_ctl.CTLbits.RTSEN = 1;
#endif #endif
#ifdef UART_1_CTS_PIN #ifdef UART_1_CTS_PIN
IOC_UARTCTS_UART1 = UART_1_CTS_PIN; gpio_init_af(UART_1_CTS_PIN, UART1_CTS, GPIO_IN);
gpio_hardware_control(UART_1_CTS_PIN);
IOC_PXX_OVER[UART_1_CTS_PIN] = IOC_OVERRIDE_DIS;
u->cc2538_uart_ctl.CTLbits.CTSEN = 1; u->cc2538_uart_ctl.CTLbits.CTSEN = 1;
#endif #endif
} }
@ -334,7 +301,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
/* Block if the TX FIFO is full */ /* Block if the TX FIFO is full */
for (size_t i = 0; i < len; i++) { for (size_t i = 0; i < len; i++) {
while (u->cc2538_uart_fr.FRbits.TXFF); while (u->cc2538_uart_fr.FRbits.TXFF) {}
u->DR = data[i]; u->DR = data[i];
} }
} }