cpu/fe310: Uncrustify code

cpu/fe310/clock.c

@@ -35,18 +35,19 @@ void clock_init(void)
         PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(4) | ROSC_TRIM(16) | ROSC_EN(1));
 
         /* Wait for HFROSC to be ready */
-        while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
+        while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) {}
 
         /* Don't use PLL clock source */
         PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(PLL_SEL_PLL);
     }
 
-    if (IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC) || IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC_PLL)) {
+    if (IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC) ||
+        IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC_PLL)) {
         /* Ensure HFXOSC is enabled */
         PRCI_REG(PRCI_HFXOSCCFG) = XOSC_EN(1);
 
         /* Wait for HFXOSC to become ready */
-        while ((PRCI_REG(PRCI_HFXOSCCFG) & XOSC_RDY(1)) == 0);
+        while ((PRCI_REG(PRCI_HFXOSCCFG) & XOSC_RDY(1)) == 0) {}
 
         /* Select HFXOSC as reference frequency and bypass PLL */
         PRCI_REG(PRCI_PLLCFG) = PLL_REFSEL(PLL_REFSEL_HFXOSC) | PLL_BYPASS(1);
@@ -56,13 +57,14 @@ void clock_init(void)
             PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
 
             /* Configure PLL */
-            PRCI_REG(PRCI_PLLCFG) |= PLL_R(CONFIG_CLOCK_PLL_R) | PLL_F(CONFIG_CLOCK_PLL_F) | PLL_Q(CONFIG_CLOCK_PLL_Q);
+            PRCI_REG(PRCI_PLLCFG) |= PLL_R(CONFIG_CLOCK_PLL_R) | PLL_F(
+                CONFIG_CLOCK_PLL_F) | PLL_Q(CONFIG_CLOCK_PLL_Q);
 
             /* Disable PLL Bypass */
             PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
 
             /* Now it is safe to check for PLL Lock */
-            while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
+            while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) {}
         }
 
         /* Switch over to PLL Clock source */
@@ -72,17 +74,20 @@ void clock_init(void)
         PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
     }
     else if (IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL)) {
-        PRCI_set_hfrosctrim_for_f_cpu(CONFIG_CLOCK_DESIRED_FREQUENCY, PRCI_FREQ_UNDERSHOOT);
+        PRCI_set_hfrosctrim_for_f_cpu(CONFIG_CLOCK_DESIRED_FREQUENCY,
+                                      PRCI_FREQ_UNDERSHOOT);
     }
     else { /* Clock HFROSC */
         /* Disable Bypass */
         PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
 
         /* Configure trim and divider values of HFROSC */
-        PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(CONFIG_CLOCK_HFROSC_DIV) | ROSC_TRIM(CONFIG_CLOCK_HFROSC_TRIM) | ROSC_EN(1));
+        PRCI_REG(PRCI_HFROSCCFG) =
+            (ROSC_DIV(CONFIG_CLOCK_HFROSC_DIV) |
+             ROSC_TRIM(CONFIG_CLOCK_HFROSC_TRIM) | ROSC_EN(1));
 
         /* Wait for HFROSC to be ready */
-        while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
+        while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) {}
 
         /* Don't use PLL clock source */
         PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(PLL_SEL_PLL);

cpu/fe310/context_frame.c

@@ -25,7 +25,8 @@
 
 
 #define CHECK_OFFSET(member)     \
-    _Static_assert(offsetof(struct context_switch_frame, member) == member ## _OFFSET, \
+    _Static_assert(offsetof(struct context_switch_frame, \
+                            member) == member ## _OFFSET, \
                    "context_switch_frame offset mismatch for offset member");
 
 static void check_context_switch_frame_alignment(void) __attribute__ ((unused));

cpu/fe310/cpu.c

@@ -83,6 +83,7 @@ void flash_init(void)
      */
     uint32_t freq = cpu_freq();
     uint32_t sckdiv = (freq - 1) / (MAX_FLASH_FREQ * 2);
+
     if (sckdiv > SCKDIV_SAFE) {
         SPI0_REG(SPI_REG_SCKDIV) = sckdiv;
     }

cpu/fe310/include/clk_conf.h

@@ -30,7 +30,8 @@ extern "C" {
  * @{
  */
 #ifndef CONFIG_USE_CLOCK_HFXOSC_PLL
-#if IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC) || IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL) || \
+#if IS_ACTIVE(CONFIG_USE_CLOCK_HFXOSC) || \
+    IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC_PLL) || \
     IS_ACTIVE(CONFIG_USE_CLOCK_HFROSC)
 #define CONFIG_USE_CLOCK_HFXOSC_PLL         0
 #else
@@ -51,22 +52,26 @@ extern "C" {
 #endif /* CONFIG_USE_CLOCK_HFROSC */
 
 #if CONFIG_USE_CLOCK_HFXOSC_PLL && \
-    (CONFIG_USE_CLOCK_HFROSC_PLL || CONFIG_USE_CLOCK_HFROSC || CONFIG_USE_CLOCK_HFXOSC)
+    (CONFIG_USE_CLOCK_HFROSC_PLL || CONFIG_USE_CLOCK_HFROSC || \
+     CONFIG_USE_CLOCK_HFXOSC)
 #error "Cannot use HFXOSC_PLL with other clock configurations"
 #endif
 
 #if CONFIG_USE_CLOCK_HFXOSC && \
-    (CONFIG_USE_CLOCK_HFROSC_PLL || CONFIG_USE_CLOCK_HFROSC || CONFIG_USE_CLOCK_HFXOSC_PLL)
+    (CONFIG_USE_CLOCK_HFROSC_PLL || CONFIG_USE_CLOCK_HFROSC || \
+     CONFIG_USE_CLOCK_HFXOSC_PLL)
 #error "Cannot use HFXOSC with other clock configurations"
 #endif
 
 #if CONFIG_USE_CLOCK_HFROSC_PLL && \
-    (CONFIG_USE_CLOCK_HFXOSC_PLL || CONFIG_USE_CLOCK_HFXOSC || CONFIG_USE_CLOCK_HFROSC)
+    (CONFIG_USE_CLOCK_HFXOSC_PLL || CONFIG_USE_CLOCK_HFXOSC || \
+     CONFIG_USE_CLOCK_HFROSC)
 #error "Cannot use HFROSC_PLL with other clock configurations"
 #endif
 
 #if CONFIG_USE_CLOCK_HFROSC && \
-    (CONFIG_USE_CLOCK_HFXOSC_PLL || CONFIG_USE_CLOCK_HFXOSC || CONFIG_USE_CLOCK_HFROSC_PLL)
+    (CONFIG_USE_CLOCK_HFXOSC_PLL || CONFIG_USE_CLOCK_HFXOSC || \
+     CONFIG_USE_CLOCK_HFROSC_PLL)
 #error "Cannot use HFROSC with other clock configurations"
 #endif
 
@@ -80,9 +85,12 @@ extern "C" {
 
 #if CONFIG_USE_CLOCK_HFXOSC_PLL
 #define CLOCK_PLL_INPUT_CLOCK               MHZ(16)
-#define CLOCK_PLL_REFR                      (CLOCK_PLL_INPUT_CLOCK / (CONFIG_CLOCK_PLL_R + 1))
+#define CLOCK_PLL_REFR                      (CLOCK_PLL_INPUT_CLOCK / \
-#define CLOCK_PLL_VCO                       (CLOCK_PLL_REFR * (2 * (CONFIG_CLOCK_PLL_F + 1)))
+                                             (CONFIG_CLOCK_PLL_R + 1))
-#define CLOCK_PLL_OUT                       (CLOCK_PLL_VCO / (1 << CONFIG_CLOCK_PLL_Q))
+#define CLOCK_PLL_VCO                       (CLOCK_PLL_REFR * \
+                                             (2 * (CONFIG_CLOCK_PLL_F + 1)))
+#define CLOCK_PLL_OUT                       (CLOCK_PLL_VCO / \
+                                             (1 << CONFIG_CLOCK_PLL_Q))
 #define CLOCK_CORECLOCK                     (CLOCK_PLL_OUT) /* 320000000Hz with the values used above */
 
 /* Check PLL settings */
@@ -90,10 +98,12 @@ extern "C" {
 #error "Only R=2 can be used when using HFXOSC"
 #endif
 #if (CLOCK_PLL_VCO < MHZ(384)) || (CLOCK_PLL_VCO > MHZ(768))
-#error "VCO frequency must be in the range [384MHz - 768MHz], check the CLOCK_PLL_F value"
+#error \
+    "VCO frequency must be in the range [384MHz - 768MHz], check the CLOCK_PLL_F value"
 #endif
 #if (CLOCK_PLL_OUT < MHZ(48)) || (CLOCK_PLL_OUT > MHZ(384))
-#error "PLL output frequency must be in the range [48MHz - 384MHz], check the CLOCK_PLL_Q value"
+#error \
+    "PLL output frequency must be in the range [48MHz - 384MHz], check the CLOCK_PLL_Q value"
 #endif
 
 #elif CONFIG_USE_CLOCK_HFXOSC

cpu/fe310/include/irq_arch.h

@@ -43,6 +43,7 @@ static inline __attribute__((always_inline)) unsigned int irq_enable(void)
 {
     /* Enable all interrupts */
     unsigned state;
+
     __asm__ volatile (
         "csrrs %[dest], mstatus, %[mask]"
         :[dest]    "=r" (state)
@@ -59,6 +60,7 @@ static inline __attribute__((always_inline)) unsigned int irq_disable(void)
 {
 
     unsigned int state;
+
     __asm__ volatile (
         "csrrc %[dest], mstatus, %[mask]"
         :[dest]    "=r" (state)
@@ -72,7 +74,8 @@ static inline __attribute__((always_inline)) unsigned int irq_disable(void)
 /**
  * @brief Restore the state of the IRQ flags
  */
-static inline __attribute__((always_inline)) void irq_restore(unsigned int state)
+static inline __attribute__((always_inline)) void irq_restore(
+    unsigned int state)
 {
     /* Restore all interrupts to given state */
     __asm__ volatile (

cpu/fe310/irq_arch.c

@@ -130,7 +130,8 @@ void handle_trap(uint32_t mcause)
 
 /* Marking this as interrupt to ensure an mret at the end, provided by the
  * compiler. Aligned to 4-byte boundary as per RISC-V spec  */
-static void __attribute((aligned(4))) __attribute__((interrupt)) trap_entry(void) {
+static void __attribute((aligned(4))) __attribute__((interrupt)) trap_entry(void)
+{
     __asm__ volatile (
         "addi sp, sp, -"XTSTR (CONTEXT_FRAME_SIZE)"          \n"
 

cpu/fe310/periph/gpio.c

@@ -108,7 +108,8 @@ void gpio_clear(gpio_t pin)
 
 void gpio_toggle(gpio_t pin)
 {
-    __atomic_fetch_xor(&GPIO_REG(GPIO_OUTPUT_VAL), (1 << pin), __ATOMIC_RELAXED);
+    __atomic_fetch_xor(&GPIO_REG(GPIO_OUTPUT_VAL), (1 << pin),
+                       __ATOMIC_RELAXED);
 }
 
 void gpio_write(gpio_t pin, int value)

cpu/fe310/periph/i2c.c

@@ -42,7 +42,8 @@ static const uint16_t _fe310_i2c_speed[2] = { 100U, 400U };
 static inline int _wait_busy(i2c_t dev, uint32_t max_timeout_counter);
 static inline int _start(i2c_t dev, uint16_t address);
 static inline int _read(i2c_t dev, uint8_t *data, int length, uint8_t stop);
-static inline int _write(i2c_t dev, const uint8_t *data, int length, uint8_t stop);
+static inline int _write(i2c_t dev, const uint8_t *data, int length,
+                         uint8_t stop);
 
 /**
  * @brief   Initialized bus locks
@@ -57,16 +58,22 @@ void i2c_init(i2c_t dev)
     mutex_init(&locks[dev]);
 
     /* Select IOF0 */
-    GPIO_REG(GPIO_IOF_SEL) &= ~((1 << i2c_config[dev].scl) | (1 << i2c_config[dev].sda));
+    GPIO_REG(GPIO_IOF_SEL) &=
+        ~((1 << i2c_config[dev].scl) | (1 << i2c_config[dev].sda));
     /* Enable IOF */
-    GPIO_REG(GPIO_IOF_EN) |= ((1 << i2c_config[dev].scl) | (1 << i2c_config[dev].sda));
+    GPIO_REG(GPIO_IOF_EN) |=
+        ((1 << i2c_config[dev].scl) | (1 << i2c_config[dev].sda));
 
-    _REG32(i2c_config[dev].addr, I2C_CONTROL) &= ~(I2C_CONTROL_IE | I2C_CONTROL_EN);
+    _REG32(i2c_config[dev].addr,
+           I2C_CONTROL) &= ~(I2C_CONTROL_IE | I2C_CONTROL_EN);
 
     /* Compute prescale: presc = (CORE_CLOCK / (5 * I2C_SPEED)) - 1 */
-    uint16_t presc = ((uint16_t)(cpu_freq() / 1000) / (5 * _fe310_i2c_speed[i2c_config[dev].speed])) - 1;
+    uint16_t presc =
+        ((uint16_t)(cpu_freq() / 1000) /
+         (5 * _fe310_i2c_speed[i2c_config[dev].speed])) - 1;
 
-    DEBUG("[i2c] init: computed prescale: %i (0x%02X|0x%02X)\n", presc, (presc >> 8), (presc & 0xFF));
+    DEBUG("[i2c] init: computed prescale: %i (0x%02X|0x%02X)\n", presc,
+          (presc >> 8), (presc & 0xFF));
 
     _REG32(i2c_config[dev].addr, I2C_PRESCALE_LO) = (presc & 0xFF);
     _REG32(i2c_config[dev].addr, I2C_PRESCALE_HI) = (presc >> 8);
@@ -114,6 +121,7 @@ int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length,
     DEBUG("[i2c] read bytes\n");
 
     int ret = 0;
+
     if (!(flags & I2C_NOSTART)) {
         ret = _start(dev, ((address << 1) | I2C_READ));
         if (ret < 0) {
@@ -134,7 +142,8 @@ int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length,
     return length;
 }
 
-int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data, size_t length,
+int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
+                    size_t length,
                     uint8_t flags)
 {
     assert(dev < I2C_NUMOF);
@@ -172,13 +181,15 @@ int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data, size_t length
 static inline int _wait_busy(i2c_t dev, uint32_t max_timeout_counter)
 {
     uint32_t timeout_counter = 0;
+
     DEBUG("[i2c] wait for transfer\n");
     while (_REG32(i2c_config[dev].addr, I2C_STATUS) & I2C_STATUS_TIP) {
         if (++timeout_counter >= max_timeout_counter) {
             DEBUG("[i2c] transfer timeout\n");
             return -ETIMEDOUT;
         }
-        else if ((_REG32(i2c_config[dev].addr, I2C_STATUS) & I2C_STATUS_ALOST) == I2C_STATUS_ALOST) {
+        else if ((_REG32(i2c_config[dev].addr,
+                         I2C_STATUS) & I2C_STATUS_ALOST) == I2C_STATUS_ALOST) {
             /* Arbitration lost */
             DEBUG("[i2c] error: Arbitration lost\n");
             return -EAGAIN;
@@ -200,6 +211,7 @@ static inline int _start(i2c_t dev, uint16_t address)
 
     /* Ensure all bytes has been read */
     int ret = _wait_busy(dev, I2C_BUSY_TIMEOUT);
+
     if (ret < 0) {
         return ret;
     }
@@ -246,7 +258,8 @@ static inline int _read(i2c_t dev, uint8_t *data, int length, uint8_t stop)
     return 0;
 }
 
-static inline int _write(i2c_t dev, const uint8_t *data, int length, uint8_t stop)
+static inline int _write(i2c_t dev, const uint8_t *data, int length,
+                         uint8_t stop)
 {
     uint8_t count = 0;
 

cpu/fe310/periph/timer.c

@@ -56,6 +56,7 @@ int timer_init(tim_t dev, uint32_t freq, timer_cb_t cb, void *arg)
 
     /* reset timer counter */
     volatile uint64_t *mtime = (uint64_t *)(CLINT_CTRL_ADDR + CLINT_MTIME);
+
     *mtime = 0;
 
     return 0;

cpu/fe310/periph/uart.c

@@ -136,8 +136,9 @@ void uart_write(uart_t dev, const uint8_t *data, size_t len)
 {
     for (size_t i = 0; i < len; i++) {
         /* Wait for FIFO to empty */
-        while ((_REG32(uart_config[dev].addr, UART_REG_TXFIFO) & UART_TXFIFO_FULL)
+        while ((_REG32(uart_config[dev].addr,
-               == (uint32_t)UART_TXFIFO_FULL) {};
+                       UART_REG_TXFIFO) & UART_TXFIFO_FULL)
+               == (uint32_t)UART_TXFIFO_FULL) {}
 
         /* Write a byte */
         _REG32(uart_config[dev].addr, UART_REG_TXFIFO) = data[i];

cpu/fe310/periph/wdt.c

@@ -59,6 +59,7 @@ void wdt_kick(void)
 static inline uint8_t _scale(uint32_t count)
 {
     uint8_t scale = 0;
+
     while (count > (UINT16_MAX - 1)) {
         count >>= 1;
         scale++;

cpu/fe310/thread_arch.c

@@ -116,6 +116,7 @@ void thread_print_stack(void)
 {
     int count = 0;
     thread_t *active_thread = thread_get_active();
+
     if (!active_thread) {
         return;
     }
@@ -206,6 +207,7 @@ void heap_stats(void)
 
     long int heap_size = &_eheap - &_sheap;
     struct mallinfo minfo = mallinfo();
+
     printf("heap: %ld (used %u, free %ld) [bytes]\n",
            heap_size, minfo.uordblks, heap_size - minfo.uordblks);
 }