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boards/nucleo32s: configure SPI

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This commit is contained in:
Alexandre Abadie 2017-04-03 10:57:12 +02:00
parent 2abce109b5
commit bab636604b
7 changed files with 123 additions and 0 deletions
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1
boards/nucleo32-f031/Makefile.features
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@ -3,6 +3,7 @@ FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_cpuid FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_uart

40
boards/nucleo32-f031/include/periph_conf.h
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@ -123,6 +123,46 @@ static const pwm_conf_t pwm_config[] = {
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */ /** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/** /**
* @name RTC configuration * @name RTC configuration
* @{ * @{

1
boards/nucleo32-f042/Makefile.features
View File

@ -3,6 +3,7 @@ FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_cpuid FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_uart

39
boards/nucleo32-f042/include/periph_conf.h
View File

@ -133,6 +133,45 @@ static const pwm_conf_t pwm_config[] = {
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */ /** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
},
{ /* for APB2 @ 48000000Hz */
7, /* -> 187500Hz */
6, /* -> 375000Hz */
5, /* -> 750000Hz */
2, /* -> 6000000Hz */
1 /* -> 12000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/** /**
* @name RTC configuration * @name RTC configuration

1
boards/nucleo32-f303/Makefile.features
View File

@ -2,6 +2,7 @@
FEATURES_PROVIDED += periph_cpuid FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_uart

40
boards/nucleo32-f303/include/periph_conf.h
View File

@ -127,6 +127,46 @@ static const pwm_conf_t pwm_config[] = {
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */ /** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 64000000Hz */
7, /* -> 250000Hz */
6, /* -> 500000Hz */
5, /* -> 1000000Hz */
3, /* -> 4000000Hz */
2 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/** /**
* @name RTC configuration * @name RTC configuration
* @{ * @{

1
boards/nucleo32-l031/Makefile.features
View File

@ -2,6 +2,7 @@
FEATURES_PROVIDED += periph_cpuid FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_uart